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authorVikram Pandita <vikram.pandita@ti.com>2011-05-31 09:24:58 +0100
committerAndy Green <andy.green@linaro.org>2011-05-31 11:06:29 +0100
commite2cc08a6988ecc3ea0a16d46bafd4646f38bbf5b (patch)
treedf48c7d3d9e96053232372ec85679116b329b428 /arch
parentcf6dc3eb7a88f5c8170b28defd272ffd9083c6f5 (diff)
ARM: L2: Add and export outer_clean_all
The Errata 588369 and 539766 demands that clean all operation be done as clean each way at a time This patch also raps the implementation under the CONFIG errata macro so that for non-errata version silicon it can be disabled Signed-off-by: Vikram Pandita <vikram.pandita@ti.com> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Woodruff, Richard <r-woodruff2@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/outercache.h8
-rw-r--r--arch/arm/mm/cache-l2x0.c1
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index d8387437ec5..fa8cbd80a3d 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -28,6 +28,7 @@ struct outer_cache_fns {
void (*clean_range)(unsigned long, unsigned long);
void (*flush_range)(unsigned long, unsigned long);
void (*flush_all)(void);
+ void (*clean_all)(void);
void (*inv_all)(void);
void (*disable)(void);
#ifdef CONFIG_OUTER_CACHE_SYNC
@@ -61,6 +62,11 @@ static inline void outer_flush_all(void)
if (outer_cache.flush_all)
outer_cache.flush_all();
}
+static inline void outer_clean_all(void)
+{
+ if (outer_cache.clean_all)
+ outer_cache.clean_all();
+}
static inline void outer_inv_all(void)
{
@@ -97,6 +103,8 @@ static inline void outer_sync(void)
#else
static inline void outer_sync(void)
{ }
+static inline void outer_clean_all(void)
+{ }
#endif
#endif /* __ASM_OUTERCACHE_H */
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index ae251209b8f..37664d60b5f 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -345,6 +345,7 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
outer_cache.inv_all = l2x0_inv_all;
outer_cache.disable = l2x0_disable;
outer_cache.set_debug = l2x0_set_debug;
+ outer_cache.clean_all = l2x0_clean_all;
printk(KERN_INFO "%s cache controller enabled\n", type);
printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",