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authorChris Wilson <chris@chris-wilson.co.uk>2010-12-08 17:32:24 +0000
committerChris Wilson <chris@chris-wilson.co.uk>2010-12-09 19:46:24 +0000
commiteb43f4af7ecb7d51ba44f5e96bf74eedf1c27d62 (patch)
tree7adf22c19151445e02efef5670b5495223396801 /drivers/gpu/drm/i915/i915_drv.h
parenta8e93126a6f10d0a14ba8407ec112b1b3a5e2e97 (diff)
drm/i915: Terminate the FORCE WAKE after we have finished reading
Once we have read the value out of the GT power well, we need to remove the FORCE WAKE bit to allow the system to auto-power down. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h21
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b8a55008a1b..30780f2cab6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1341,17 +1341,20 @@ __i915_write(64, q)
* must be set to prevent GT core from power down and stale values being
* returned.
*/
+void __gen6_force_wake_get(struct drm_i915_private *dev_priv);
+void __gen6_force_wake_put (struct drm_i915_private *dev_priv);
static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
{
- if (IS_GEN6(dev_priv->dev)) {
- I915_WRITE_NOTRACE(FORCEWAKE, 1);
- POSTING_READ(FORCEWAKE);
- /* XXX How long do we really need to wait here?
- * Will different registers/engines require different periods?
- */
- udelay(100);
- }
- return I915_READ(reg);
+ u32 val;
+
+ if (dev_priv->info->gen >= 6) {
+ __gen6_force_wake_get(dev_priv);
+ val = I915_READ(reg);
+ __gen6_force_wake_put(dev_priv);
+ } else
+ val = I915_READ(reg);
+
+ return val;
}
static inline void