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authorAlex Deucher <alexdeucher@gmail.com>2010-10-21 13:31:38 -0400
committerDave Airlie <airlied@redhat.com>2010-10-26 14:42:39 +1000
commit2281a378e1830d7ab78d3067f228e4e55d368b0d (patch)
tree8fce4594a1d1b8854d219f5297ccb5ecfc263b10 /drivers/gpu/drm/radeon/evergreend.h
parentc3cceeddf0b5f97b0d2352b98ef0f025e31a9ae3 (diff)
drm/radeon/kms/evergreen: set the clear state to the blit state
The hw stores a default clear state for registers in the context range that can be initialized when the CP is set up. Set the blit state as the default clear state and use the CLEAR_STATE packet to load the blit state rather than loading it from an IB. This reduces overhead when doing bo moves using the 3D engine. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index d507f438eed..113c70cc8b3 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -658,6 +658,8 @@
#define PACKET3_EVENT_WRITE_EOP 0x47
#define PACKET3_EVENT_WRITE_EOS 0x48
#define PACKET3_PREAMBLE_CNTL 0x4A
+# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
+# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
#define PACKET3_RB_OFFSET 0x4B
#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D