arm: ux500: common dbx500 prcmu driver api

This patch updates the PRCMU driver API to be the same
(as far as possible) in U8500 and U4500.

- <mach/prcmu-fw-api.h> has been renamed <mach/prcmu.h>.
- The platform specific APIs have moved to <mach/prcmu-db5500.h>
  and <mach/prcmu-db8500.h> (but these should not be directly
  included).
- The PRCMU QoS API has been put in <mach/prcmu-qos.h>.

ST Ericsson ID: 334772
ST Ericsson FOSS-OUT ID: trivial
ST Ericsson Linux next: 318371

Change-Id: I6ce117ec35ebf2e987178ccacce09afb554d2736
Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/23863
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>

33 files changed, 823 insertions, 1073 deletions

diff --git a/arch/arm/mach-ux500/clock-db5500.c b/arch/arm/mach-ux500/clock-db5500.c
index ca93c009c25..f1e68441fae 100644
--- a/arch/arm/mach-ux500/clock-db5500.c
+++ b/arch/arm/mach-ux500/clock-db5500.c
@@ -24,11 +24,10 @@
 #include <plat/pincfg.h>
 
 #include <mach/hardware.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #include "clock.h"
 #include "pins-db5500.h"
-#include "prcmu-db5500.h"
 #include "prcmu-regs-db5500.h"
 
 static DEFINE_MUTEX(sysclk_mutex);
@@ -60,7 +59,7 @@ static int request_sysclk(bool enable)
 	static int requests;
 
 	if ((enable && (requests++ == 0)) || (!enable && (--requests == 0)))
-		return db5500_prcmu_request_clock(DB5500_PRCMU_SYSCLK, enable);
+		return prcmu_request_clock(DB5500_PRCMU_SYSCLK, enable);
 	return 0;
 }
 
@@ -799,12 +798,12 @@ static void __init db5500_boot_clk_enable(void)
 
 static int db5500_prcmu_clk_enable(struct clk *clk)
 {
-	return db5500_prcmu_request_clock(clk->cg_sel, true);
+	return prcmu_request_clock(clk->cg_sel, true);
 }
 
 static void db5500_prcmu_clk_disable(struct clk *clk)
 {
-	if (db5500_prcmu_request_clock(clk->cg_sel, false)) {
+	if (prcmu_request_clock(clk->cg_sel, false)) {
 		pr_err("clock: %s failed to disable %s.\n", __func__,
 			clk->name);
 	}
diff --git a/arch/arm/mach-ux500/clock-db8500.c b/arch/arm/mach-ux500/clock-db8500.c
index d4f33f9bd55..58bd646b478 100644
--- a/arch/arm/mach-ux500/clock-db8500.c
+++ b/arch/arm/mach-ux500/clock-db8500.c
@@ -27,7 +27,7 @@
 #include <plat/pincfg.h>
 
 #include <mach/hardware.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #include "clock.h"
 #include "pins-db8500.h"
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 5f52ec29043..b6fbd9eb3c7 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -19,7 +19,7 @@
 #include <linux/kernel.h>
 #endif
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index a8a294aa6c7..d98e7e1d882 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -25,7 +25,7 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <mach/reboot_reasons.h>
 #include <mach/usb.h>
 #include <mach/ste-dma40-db8500.h>
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 1086d1684d2..7ad3861aa50 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -22,8 +22,7 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
-#include <mach/prcmu-fw-api.h>
-#include <mach/prcmu-db5500.h>
+#include <mach/prcmu.h>
 #include <mach/reboot_reasons.h>
 
 #include "clock.h"
diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c
index 8af7e7ba4b4..9e2478023e9 100644
--- a/arch/arm/mach-ux500/devices-db5500.c
+++ b/arch/arm/mach-ux500/devices-db5500.c
@@ -20,7 +20,7 @@
 #include <video/mcde.h>
 #include <mach/db5500-regs.h>
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #define GPIO_DATA(_name, first, num)					\
 	{								\
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index dde1cfd66fd..2cb11006b7d 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -24,7 +24,7 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <video/mcde.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <mach/prcmu-regs.h>
 #include <mach/hsi.h>
 #include <mach/ste-dma40-db8500.h>
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-db5500.h b/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
index 7e745a116af..dc1f1fa8bb8 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
@@ -8,6 +8,37 @@
 #ifndef __MACH_PRCMU_U5500_H
 #define __MACH_PRCMU_U5500_H
 
+/*
+ * Clock identifiers.
+ */
+enum db5500_prcmu_clock {
+	DB5500_PRCMU_SGACLK,
+	DB5500_PRCMU_UARTCLK,
+	DB5500_PRCMU_MSP02CLK,
+	DB5500_PRCMU_I2CCLK,
+	DB5500_PRCMU_SDMMCCLK,
+	DB5500_PRCMU_PER1CLK,
+	DB5500_PRCMU_PER2CLK,
+	DB5500_PRCMU_PER3CLK,
+	DB5500_PRCMU_PER5CLK,
+	DB5500_PRCMU_PER6CLK,
+	DB5500_PRCMU_PWMCLK,
+	DB5500_PRCMU_IRDACLK,
+	DB5500_PRCMU_IRRCCLK,
+	DB5500_PRCMU_HDMICLK,
+	DB5500_PRCMU_APEATCLK,
+	DB5500_PRCMU_APETRACECLK,
+	DB5500_PRCMU_MCDECLK,
+	DB5500_PRCMU_DSIALTCLK,
+	DB5500_PRCMU_DMACLK,
+	DB5500_PRCMU_B2R2CLK,
+	DB5500_PRCMU_TVCLK,
+	DB5500_PRCMU_RNGCLK,
+	DB5500_PRCMU_NUM_REG_CLOCKS,
+	DB5500_PRCMU_SYSCLK = DB5500_PRCMU_NUM_REG_CLOCKS,
+	DB5500_PRCMU_TIMCLK,
+};
+
 #ifdef CONFIG_UX500_SOC_DB5500
 
 void db5500_prcmu_early_init(void);
@@ -15,8 +46,28 @@ void db5500_prcmu_early_init(void);
 int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
 int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
 
+int db5500_prcmu_request_clock(u8 clock, bool enable);
+
 int prcmu_resetout(u8 resoutn, u8 state);
 
+static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+	bool keep_ap_pll)
+{
+	return 0;
+}
+
+static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
+{
+	return 0;
+}
+
+static inline int prcmu_request_clock(u8 clock, bool enable)
+{
+	return db5500_prcmu_request_clock(clock, enable);
+}
+
+static inline void prcmu_system_reset(u16 reset_code) {}
+
 #else /* !CONFIG_UX500_SOC_DB5500 */
 
 static inline void db5500_prcmu_early_init(void)
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-db8500.h b/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
new file mode 100644
index 00000000000..f5efd0d369c
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
@@ -0,0 +1,308 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * U8500 specific PRCMU API.
+ */
+#ifndef __MACH_PRCMU_DB8500_H
+#define __MACH_PRCMU_DB8500_H
+
+/*
+ * Definitions for autonomous power management configuration.
+ */
+
+#define PRCMU_AUTO_PM_OFF 0
+#define PRCMU_AUTO_PM_ON 1
+
+#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
+#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
+
+enum prcmu_auto_pm_policy {
+	PRCMU_AUTO_PM_POLICY_NO_CHANGE,
+	PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
+	PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
+	PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
+	PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
+};
+
+/**
+ * struct prcmu_auto_pm_config - Autonomous power management configuration.
+ * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
+ * @sia_power_on:       SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
+ * @sia_policy:         SIA power policy. (enum prcmu_auto_pm_policy)
+ * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
+ * @sva_power_on:       SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
+ * @sva_policy:         SVA power policy. (enum prcmu_auto_pm_policy)
+ */
+struct prcmu_auto_pm_config {
+	u8 sia_auto_pm_enable;
+	u8 sia_power_on;
+	u8 sia_policy;
+	u8 sva_auto_pm_enable;
+	u8 sva_power_on;
+	u8 sva_policy;
+};
+
+/**
+ * enum hw_acc_dev - enum for hw accelerators
+ * @HW_ACC_SVAMMDSP: for SVAMMDSP
+ * @HW_ACC_SVAPIPE:  for SVAPIPE
+ * @HW_ACC_SIAMMDSP: for SIAMMDSP
+ * @HW_ACC_SIAPIPE: for SIAPIPE
+ * @HW_ACC_SGA: for SGA
+ * @HW_ACC_B2R2: for B2R2
+ * @HW_ACC_MCDE: for MCDE
+ * @HW_ACC_ESRAM1: for ESRAM1
+ * @HW_ACC_ESRAM2: for ESRAM2
+ * @HW_ACC_ESRAM3: for ESRAM3
+ * @HW_ACC_ESRAM4: for ESRAM4
+ * @NUM_HW_ACC: number of hardware accelerators
+ *
+ * Different hw accelerators which can be turned ON/
+ * OFF or put into retention (MMDSPs and ESRAMs).
+ * Used with EPOD API.
+ *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
+ */
+enum hw_acc_dev{
+	HW_ACC_SVAMMDSP,
+	HW_ACC_SVAPIPE,
+	HW_ACC_SIAMMDSP,
+	HW_ACC_SIAPIPE,
+	HW_ACC_SGA,
+	HW_ACC_B2R2,
+	HW_ACC_MCDE,
+	HW_ACC_ESRAM1,
+	HW_ACC_ESRAM2,
+	HW_ACC_ESRAM3,
+	HW_ACC_ESRAM4,
+	NUM_HW_ACC
+};
+
+/*
+ * Definitions for controlling ESRAM0 in deep sleep.
+ */
+#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
+#define ESRAM0_DEEP_SLEEP_STATE_RET 2
+
+/**
+ * enum ddr_pwrst - DDR power states definition
+ * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
+ * @DDR_PWR_STATE_ON:
+ * @DDR_PWR_STATE_OFFLOWLAT:
+ * @DDR_PWR_STATE_OFFHIGHLAT:
+ */
+enum ddr_pwrst {
+	DDR_PWR_STATE_UNCHANGED     = 0x00,
+	DDR_PWR_STATE_ON            = 0x01,
+	DDR_PWR_STATE_OFFLOWLAT     = 0x02,
+	DDR_PWR_STATE_OFFHIGHLAT    = 0x03
+};
+
+/**
+ * enum hw_acc_state - State definition for hardware accelerator
+ * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
+ * @HW_OFF: The hardware accelerator must be switched off
+ * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
+ *               internal RAM in retention
+ * @HW_ON: The hwa hardware accelerator hwa must be switched on
+ *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
+ */
+enum hw_acc_state {
+	HW_NO_CHANGE = 0x00,
+	HW_OFF = 0x01,
+	HW_OFF_RAMRET = 0x02,
+	HW_ON = 0x04
+};
+
+/**
+ * enum romcode_write - Romcode message written by A9 AND read by XP70
+ * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
+ * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
+ *                 romcode. The xp70 will go into self-reset
+ */
+enum romcode_write {
+	RDY_2_DS = 0x09,
+	RDY_2_XP70_RST = 0x10
+};
+
+/**
+ * enum romcode_read - Romcode message written by XP70 and read by A9
+ * @INIT: Init value when romcode field is not used
+ * @FS_2_DS: Value set when power state is going from ApExecute to
+ *          ApDeepSleep
+ * @END_DS: Value set when ApDeepSleep power state is reached coming from
+ *         ApExecute state
+ * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
+ *           ApExecute
+ * @END_FS: Value set when ApExecute power state is reached coming from
+ *         ApDeepSleep state
+ * @SWR: Value set when power state is going to ApReset
+ * @END_SWR: Value set when the xp70 finished executing ApReset actions and
+ *          waits for romcode acknowledgment to go to self-reset
+ */
+enum romcode_read {
+	INIT = 0x00,
+	FS_2_DS = 0x0A,
+	END_DS = 0x0B,
+	DS_TO_FS = 0x0C,
+	END_FS = 0x0D,
+	SWR = 0x0E,
+	END_SWR = 0x0F
+};
+
+/**
+ * enum ap_pwrst - current power states defined in PRCMU firmware
+ * @NO_PWRST: Current power state init
+ * @AP_BOOT: Current power state is apBoot
+ * @AP_EXECUTE: Current power state is apExecute
+ * @AP_DEEP_SLEEP: Current power state is apDeepSleep
+ * @AP_SLEEP: Current power state is apSleep
+ * @AP_IDLE: Current power state is apIdle
+ * @AP_RESET: Current power state is apReset
+ */
+enum ap_pwrst {
+	NO_PWRST = 0x00,
+	AP_BOOT = 0x01,
+	AP_EXECUTE = 0x02,
+	AP_DEEP_SLEEP = 0x03,
+	AP_SLEEP = 0x04,
+	AP_IDLE = 0x05,
+	AP_RESET = 0x06
+};
+
+#ifdef CONFIG_UX500_SOC_DB8500
+
+bool prcmu_is_u8400(void);
+
+int prcmu_request_ape_opp_100_voltage(bool enable);
+
+int prcmu_release_usb_wakeup_state(void);
+
+int prcmu_set_clock_divider(u8 clock, u8 divider);
+
+void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+	struct prcmu_auto_pm_config *idle);
+bool prcmu_is_auto_pm_enabled(void);
+
+/* NOTE! Use regulator framework instead */
+int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
+
+/* TODO: Check if anyone is using these. */
+int prcmu_set_rc_a2p(enum romcode_write);
+enum romcode_read prcmu_get_rc_p2a(void);
+enum ap_pwrst prcmu_get_xp70_current_state(void);
+
+/* TODO: Common API with DB5500? */
+int prcmu_config_esram0_deep_sleep(u8 state);
+bool prcmu_has_arm_maxopp(void);
+void prcmu_config_abb_event_readout(u32 abb_events);
+void prcmu_get_abb_event_buffer(void __iomem **buf);
+int prcmu_config_hotdog(u8 threshold);
+int prcmu_config_hotmon(u8 low, u8 high);
+int prcmu_start_temp_sense(u16 cycles32k);
+int prcmu_stop_temp_sense(void);
+void prcmu_enable_spi2(void);
+void prcmu_disable_spi2(void);
+
+#else /* !CONFIG_UX500_SOC_DB8500 */
+
+static inline bool prcmu_is_u8400(void)
+{
+	return false;
+}
+
+static inline int prcmu_request_ape_opp_100_voltage(bool enable)
+{
+	return 0;
+}
+
+static inline int prcmu_release_usb_wakeup_state(void)
+{
+	return 0;
+}
+
+static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
+{
+	return 0;
+}
+
+static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+	struct prcmu_auto_pm_config *idle)
+{
+}
+
+static inline bool prcmu_is_auto_pm_enabled(void)
+{
+	return false;
+}
+
+static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
+{
+	return 0;
+}
+
+static inline int prcmu_set_rc_a2p(enum romcode_write code)
+{
+	return 0;
+}
+
+static inline enum romcode_read prcmu_get_rc_p2a(void)
+{
+	return INIT;
+}
+
+static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
+{
+	return AP_EXECUTE;
+}
+
+static inline int prcmu_config_esram0_deep_sleep(u8 state)
+{
+	return 0;
+}
+
+static inline bool prcmu_has_arm_maxopp(void)
+{
+	return false;
+}
+
+static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
+
+static inline int prcmu_config_hotdog(u8 threshold)
+{
+	return 0;
+}
+
+static inline int prcmu_config_hotmon(u8 low, u8 high)
+{
+	return 0;
+}
+
+static inline int prcmu_start_temp_sense(u16 cycles32k)
+{
+	return 0;
+}
+
+static inline int prcmu_stop_temp_sense(void)
+{
+	return 0;
+}
+
+static inline int prcmu_enable_spi2(void)
+{
+	return 0;
+}
+
+static inline int prcmu_disable_spi2(void)
+{
+	return 0;
+}
+
+#endif /* CONFIG_UX500_SOC_DB8500 */
+
+#endif /* __MACH_PRCMU_DB8500_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h
index 2b593272f09..7995ed1f77f 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h
@@ -10,529 +10,7 @@
 #ifndef __MACH_PRCMU_FW_API_H
 #define __MACH_PRCMU_FW_API_H
 
-#include <linux/interrupt.h>
-#include <linux/notifier.h>
-#include "prcmu-fw-defs_v1.h"
+#warning <mach/prcmu-fw-api.h> has been replaced by <mach/prcmu.h>
+#include <mach/prcmu.h>
 
-/* PRCMU Wakeup defines */
-enum prcmu_wakeup_index {
-	PRCMU_WAKEUP_INDEX_RTC,
-	PRCMU_WAKEUP_INDEX_RTT0,
-	PRCMU_WAKEUP_INDEX_RTT1,
-	PRCMU_WAKEUP_INDEX_HSI0,
-	PRCMU_WAKEUP_INDEX_HSI1,
-	PRCMU_WAKEUP_INDEX_USB,
-	PRCMU_WAKEUP_INDEX_ABB,
-	PRCMU_WAKEUP_INDEX_ABB_FIFO,
-	PRCMU_WAKEUP_INDEX_ARM,
-	NUM_PRCMU_WAKEUP_INDICES
-};
-#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
-
-/* PRCMU QoS APE OPP class */
-#define PRCMU_QOS_APE_OPP 1
-#define PRCMU_QOS_DDR_OPP 2
-#define PRCMU_QOS_DEFAULT_VALUE -1
-
-/**
- * enum hw_acc_dev - enum for hw accelerators
- * @HW_ACC_SVAMMDSP: for SVAMMDSP
- * @HW_ACC_SVAPIPE:  for SVAPIPE
- * @HW_ACC_SIAMMDSP: for SIAMMDSP
- * @HW_ACC_SIAPIPE: for SIAPIPE
- * @HW_ACC_SGA: for SGA
- * @HW_ACC_B2R2: for B2R2
- * @HW_ACC_MCDE: for MCDE
- * @HW_ACC_ESRAM1: for ESRAM1
- * @HW_ACC_ESRAM2: for ESRAM2
- * @HW_ACC_ESRAM3: for ESRAM3
- * @HW_ACC_ESRAM4: for ESRAM4
- * @NUM_HW_ACC: number of hardware accelerators
- *
- * Different hw accelerators which can be turned ON/
- * OFF or put into retention (MMDSPs and ESRAMs).
- * Used with EPOD API.
- *
- * NOTE! Deprecated, to be removed when all users switched over to use the
- * regulator API.
- */
-enum hw_acc_dev{
-	HW_ACC_SVAMMDSP,
-	HW_ACC_SVAPIPE,
-	HW_ACC_SIAMMDSP,
-	HW_ACC_SIAPIPE,
-	HW_ACC_SGA,
-	HW_ACC_B2R2,
-	HW_ACC_MCDE,
-	HW_ACC_ESRAM1,
-	HW_ACC_ESRAM2,
-	HW_ACC_ESRAM3,
-	HW_ACC_ESRAM4,
-	NUM_HW_ACC
-};
-
-/*
- * Ids for all EPODs (power domains)
- * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
- * - EPOD_ID_SVAPIPE: power domain for SVA pipe
- * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
- * - EPOD_ID_SIAPIPE: power domain for SIA pipe
- * - EPOD_ID_SGA: power domain for SGA
- * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
- * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
- * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
- * - NUM_EPOD_ID: number of power domains
- */
-#define EPOD_ID_SVAMMDSP	0
-#define EPOD_ID_SVAPIPE		1
-#define EPOD_ID_SIAMMDSP	2
-#define EPOD_ID_SIAPIPE		3
-#define EPOD_ID_SGA		4
-#define EPOD_ID_B2R2_MCDE	5
-#define EPOD_ID_ESRAM12		6
-#define EPOD_ID_ESRAM34		7
-#define NUM_EPOD_ID		8
-
-/*
- * state definition for EPOD (power domain)
- * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
- * - EPOD_STATE_OFF: The EPOD is switched off
- * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
- *                         retention
- * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
- * - EPOD_STATE_ON: Same as above, but with clock enabled
- */
-#define EPOD_STATE_NO_CHANGE	0x00
-#define EPOD_STATE_OFF		0x01
-#define EPOD_STATE_RAMRET	0x02
-#define EPOD_STATE_ON_CLK_OFF	0x03
-#define EPOD_STATE_ON		0x04
-
-/*
- * CLKOUT sources
- */
-#define PRCMU_CLKSRC_CLK38M		0x00
-#define PRCMU_CLKSRC_ACLK		0x01
-#define PRCMU_CLKSRC_SYSCLK		0x02
-#define PRCMU_CLKSRC_LCDCLK		0x03
-#define PRCMU_CLKSRC_SDMMCCLK		0x04
-#define PRCMU_CLKSRC_TVCLK		0x05
-#define PRCMU_CLKSRC_TIMCLK		0x06
-#define PRCMU_CLKSRC_CLK009		0x07
-/* These are only valid for CLKOUT1: */
-#define PRCMU_CLKSRC_SIAMMDSPCLK	0x40
-#define PRCMU_CLKSRC_I2CCLK		0x41
-#define PRCMU_CLKSRC_MSP02CLK		0x42
-#define PRCMU_CLKSRC_ARMPLL_OBSCLK	0x43
-#define PRCMU_CLKSRC_HSIRXCLK		0x44
-#define PRCMU_CLKSRC_HSITXCLK		0x45
-#define PRCMU_CLKSRC_ARMCLKFIX		0x46
-#define PRCMU_CLKSRC_HDMICLK		0x47
-
-/*
- * Definitions for autonomous power management configuration.
- */
-
-#define PRCMU_AUTO_PM_OFF 0
-#define PRCMU_AUTO_PM_ON 1
-
-#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
-#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
-
-enum prcmu_auto_pm_policy {
-	PRCMU_AUTO_PM_POLICY_NO_CHANGE,
-	PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
-	PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
-	PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
-	PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
-};
-
-/**
- * struct prcmu_auto_pm_config - Autonomous power management configuration.
- * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
- * @sia_power_on:       SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
- * @sia_policy:         SIA power policy. (enum prcmu_auto_pm_policy)
- * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
- * @sva_power_on:       SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
- * @sva_policy:         SVA power policy. (enum prcmu_auto_pm_policy)
- */
-struct prcmu_auto_pm_config {
-	u8 sia_auto_pm_enable;
-	u8 sia_power_on;
-	u8 sia_policy;
-	u8 sva_auto_pm_enable;
-	u8 sva_power_on;
-	u8 sva_policy;
-};
-
-/**
- * enum ddr_opp - DDR OPP states definition
- * @DDR_100_OPP: The new DDR operating point is ddr100opp
- * @DDR_50_OPP: The new DDR operating point is ddr50opp
- * @DDR_25_OPP: The new DDR operating point is ddr25opp
- */
-enum ddr_opp {
-	DDR_100_OPP = 0x00,
-	DDR_50_OPP = 0x01,
-	DDR_25_OPP = 0x02,
-};
-
-/*
- * Clock identifiers.
- */
-enum prcmu_clock {
-	PRCMU_SGACLK,
-	PRCMU_UARTCLK,
-	PRCMU_MSP02CLK,
-	PRCMU_MSP1CLK,
-	PRCMU_I2CCLK,
-	PRCMU_SDMMCCLK,
-	PRCMU_SLIMCLK,
-	PRCMU_PER1CLK,
-	PRCMU_PER2CLK,
-	PRCMU_PER3CLK,
-	PRCMU_PER5CLK,
-	PRCMU_PER6CLK,
-	PRCMU_PER7CLK,
-	PRCMU_LCDCLK,
-	PRCMU_BMLCLK,
-	PRCMU_HSITXCLK,
-	PRCMU_HSIRXCLK,
-	PRCMU_HDMICLK,
-	PRCMU_APEATCLK,
-	PRCMU_APETRACECLK,
-	PRCMU_MCDECLK,
-	PRCMU_IPI2CCLK,
-	PRCMU_DSIALTCLK,
-	PRCMU_DMACLK,
-	PRCMU_B2R2CLK,
-	PRCMU_TVCLK,
-	PRCMU_SSPCLK,
-	PRCMU_RNGCLK,
-	PRCMU_UICCCLK,
-	PRCMU_NUM_REG_CLOCKS,
-	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
-	PRCMU_PLLSOC1,
-	PRCMU_TIMCLK,
-};
-
-/*
- * Definitions for controlling ESRAM0 in deep sleep.
- */
-#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
-#define ESRAM0_DEEP_SLEEP_STATE_RET 2
-
-#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
-void __init prcmu_early_init(void);
-int prcmu_set_display_clocks(void);
-int prcmu_disable_dsipll(void);
-int prcmu_enable_dsipll(void);
-#else
-static inline void __init prcmu_early_init(void) {}
-#endif
-
-#ifdef CONFIG_UX500_SOC_DB8500
-
-int prcmu_set_rc_a2p(enum romcode_write);
-enum romcode_read prcmu_get_rc_p2a(void);
-enum ap_pwrst prcmu_get_xp70_current_state(void);
-int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
-
-void prcmu_enable_wakeups(u32 wakeups);
-static inline void prcmu_disable_wakeups(void)
-{
-	prcmu_enable_wakeups(0);
-}
-
-void prcmu_config_abb_event_readout(u32 abb_events);
-void prcmu_get_abb_event_buffer(void __iomem **buf);
-int prcmu_set_arm_opp(u8 opp);
-int prcmu_get_arm_opp(void);
-bool prcmu_has_arm_maxopp(void);
-bool prcmu_is_u8400(void);
-int prcmu_set_ape_opp(u8 opp);
-int prcmu_get_ape_opp(void);
-int prcmu_request_ape_opp_100_voltage(bool enable);
-int prcmu_release_usb_wakeup_state(void);
-int prcmu_set_ddr_opp(u8 opp);
-int prcmu_get_ddr_opp(void);
-unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
-void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
-void prcmu_qos_force_opp(int, s32);
-/* NOTE! Use regulator framework instead */
-int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
-int prcmu_set_epod(u16 epod_id, u8 epod_state);
-void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
-	struct prcmu_auto_pm_config *idle);
-bool prcmu_is_auto_pm_enabled(void);
-
-int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
-int prcmu_request_clock(u8 clock, bool enable);
-int prcmu_set_clock_divider(u8 clock, u8 divider);
-int prcmu_config_esram0_deep_sleep(u8 state);
-int prcmu_config_hotdog(u8 threshold);
-int prcmu_config_hotmon(u8 low, u8 high);
-int prcmu_start_temp_sense(u16 cycles32k);
-int prcmu_stop_temp_sense(void);
-int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
-
-void prcmu_ac_wake_req(void);
-void prcmu_ac_sleep_req(void);
-void prcmu_system_reset(u16 reset_code);
-u16 prcmu_get_reset_code(void);
-void prcmu_modem_reset(void);
-bool prcmu_is_ac_wake_requested(void);
-void prcmu_enable_spi2(void);
-void prcmu_disable_spi2(void);
-
-#else /* !CONFIG_UX500_SOC_DB8500 */
-
-static inline int prcmu_set_rc_a2p(enum romcode_write code)
-{
-	return 0;
-}
-
-static inline enum romcode_read prcmu_get_rc_p2a(void)
-{
-	return INIT;
-}
-
-static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
-{
-	return AP_EXECUTE;
-}
-
-static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
-	bool keep_ap_pll)
-{
-	return 0;
-}
-
-static inline void prcmu_enable_wakeups(u32 wakeups) {}
-
-static inline void prcmu_disable_wakeups(void) {}
-
-static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
-
-static inline int prcmu_set_arm_opp(u8 opp)
-{
-	return 0;
-}
-
-static inline int prcmu_get_arm_opp(void)
-{
-	return ARM_100_OPP;
-}
-
-static inline bool prcmu_has_arm_maxopp(void)
-{
-	return false;
-}
-
-static inline bool prcmu_is_u8400(void)
-{
-	return false;
-}
-
-static inline int prcmu_set_ape_opp(u8 opp)
-{
-	return 0;
-}
-
-static inline int prcmu_get_ape_opp(void)
-{
-	return APE_100_OPP;
-}
-
-static inline int prcmu_request_ape_opp_100_voltage(bool enable)
-{
-	return 0;
-}
-
-static inline int prcmu_release_usb_wakeup_state(void)
-{
-	return 0;
-}
-
-static inline int prcmu_set_ddr_opp(u8 opp)
-{
-	return 0;
-}
-
-static inline int prcmu_get_ddr_opp(void)
-{
-	return DDR_100_OPP;
-}
-
-static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
-{
-	return 0;
-}
-
-static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
-
-static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
-
-static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
-{
-	return 0;
-}
-
-static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
-	struct prcmu_auto_pm_config *idle)
-{
-}
-
-static inline bool prcmu_is_auto_pm_enabled(void)
-{
-	return false;
-}
-
-static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
-{
-	return 0;
-}
-
-static inline int prcmu_request_clock(u8 clock, bool enable)
-{
-	return 0;
-}
-
-static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
-{
-	return 0;
-}
-
-static inline int prcmu_config_esram0_deep_sleep(u8 state)
-{
-	return 0;
-}
-
-static inline int prcmu_config_hotdog(u8 threshold)
-{
-	return 0;
-}
-
-static inline int prcmu_config_hotmon(u8 low, u8 high)
-{
-	return 0;
-}
-
-static inline int prcmu_start_temp_sense(u16 cycles32k)
-{
-	return 0;
-}
-
-static inline int prcmu_stop_temp_sense(void)
-{
-	return 0;
-}
-
-static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
-{
-	return -ENOSYS;
-}
-
-static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
-{
-	return -ENOSYS;
-}
-
-static inline void prcmu_ac_wake_req(void) {}
-
-static inline void prcmu_ac_sleep_req(void) {}
-
-static inline void prcmu_system_reset(u16 reset_code) {}
-
-static inline u16 prcmu_get_reset_code(void)
-{
-	return 0;
-}
-
-static inline void prcmu_modem_reset(void) {}
-
-static inline bool prcmu_is_ac_wake_requested(void)
-{
-	return false;
-}
-
-static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
-{
-	return 0;
-}
-
-#ifndef CONFIG_UX500_SOC_DB5500
-static inline int prcmu_set_display_clocks(void)
-{
-	return 0;
-}
-
-static inline int prcmu_disable_dsipll(void)
-{
-	return 0;
-}
-
-static inline int prcmu_enable_dsipll(void)
-{
-	return 0;
-}
-#endif
-
-static inline int prcmu_enable_spi2(void)
-{
-	return 0;
-}
-
-static inline int prcmu_disable_spi2(void)
-{
-	return 0;
-}
-
-#endif /* !CONFIG_UX500_SOC_DB5500 */
-
-#ifdef CONFIG_UX500_PRCMU_QOS_POWER
-int prcmu_qos_requirement(int pm_qos_class);
-int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
-int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
-void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
-int prcmu_qos_add_notifier(int prcmu_qos_class,
-			   struct notifier_block *notifier);
-int prcmu_qos_remove_notifier(int prcmu_qos_class,
-			      struct notifier_block *notifier);
-#else
-static inline int prcmu_qos_requirement(int prcmu_qos_class)
-{
-	return 0;
-}
-
-static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
-					    char *name, s32 value)
-{
-	return 0;
-}
-
-static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
-					       char *name, s32 new_value)
-{
-	return 0;
-}
-
-static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
-{
-}
-
-static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
-					 struct notifier_block *notifier)
-{
-	return 0;
-}
-static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
-					    struct notifier_block *notifier)
-{
-	return 0;
-}
-
-#endif
-
-#endif /* __MACH_PRCMU_FW_API_V1_H */
+#endif /* __MACH_PRCMU_FW_API_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h
deleted file mode 100644
index 42a8cd2310f..00000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-fw-defs_v1.h
+++ /dev/null
@@ -1,467 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- *
- * PRCMU definitions for U8500 v1.0 cut
- */
-#ifndef __MACH_PRCMU_FW_DEFS_V1_H
-#define __MACH_PRCMU_FW_DEFS_V1_H
-
-#include <linux/interrupt.h>
-
-/**
- * enum state - ON/OFF state definition
- * @OFF: State is ON
- * @ON: State is OFF
- *
- */
-enum state {
-	OFF = 0x0,
-	ON  = 0x1,
-};
-
-/**
- * enum ret_state - general purpose On/Off/Retention states
- *
- */
-enum ret_state {
-	OFFST = 0,
-	ONST  = 1,
-	RETST = 2
-};
-
-/**
- * enum clk_arm - ARM Cortex A9 clock schemes
- * @A9_OFF:
- * @A9_BOOT:
- * @A9_OPPT1:
- * @A9_OPPT2:
- * @A9_EXTCLK:
- */
-enum clk_arm {
-	A9_OFF,
-	A9_BOOT,
-	A9_OPPT1,
-	A9_OPPT2,
-	A9_EXTCLK
-};
-
-/**
- * enum clk_gen - GEN#0/GEN#1 clock schemes
- * @GEN_OFF:
- * @GEN_BOOT:
- * @GEN_OPPT1:
- */
-enum clk_gen {
-	GEN_OFF,
-	GEN_BOOT,
-	GEN_OPPT1,
-};
-
-/* some information between arm and xp70 */
-
-/**
- * enum romcode_write - Romcode message written by A9 AND read by XP70
- * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
- * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
- *                 romcode. The xp70 will go into self-reset
- */
-enum romcode_write {
-	RDY_2_DS = 0x09,
-	RDY_2_XP70_RST = 0x10
-};
-
-/**
- * enum romcode_read - Romcode message written by XP70 and read by A9
- * @INIT: Init value when romcode field is not used
- * @FS_2_DS: Value set when power state is going from ApExecute to
- *          ApDeepSleep
- * @END_DS: Value set when ApDeepSleep power state is reached coming from
- *         ApExecute state
- * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
- *           ApExecute
- * @END_FS: Value set when ApExecute power state is reached coming from
- *         ApDeepSleep state
- * @SWR: Value set when power state is going to ApReset
- * @END_SWR: Value set when the xp70 finished executing ApReset actions and
- *          waits for romcode acknowledgment to go to self-reset
- */
-enum romcode_read {
-	INIT = 0x00,
-	FS_2_DS = 0x0A,
-	END_DS = 0x0B,
-	DS_TO_FS = 0x0C,
-	END_FS = 0x0D,
-	SWR = 0x0E,
-	END_SWR = 0x0F
-};
-
-/**
- * enum ap_pwrst - current power states defined in PRCMU firmware
- * @NO_PWRST: Current power state init
- * @AP_BOOT: Current power state is apBoot
- * @AP_EXECUTE: Current power state is apExecute
- * @AP_DEEP_SLEEP: Current power state is apDeepSleep
- * @AP_SLEEP: Current power state is apSleep
- * @AP_IDLE: Current power state is apIdle
- * @AP_RESET: Current power state is apReset
- */
-enum ap_pwrst {
-	NO_PWRST = 0x00,
-	AP_BOOT = 0x01,
-	AP_EXECUTE = 0x02,
-	AP_DEEP_SLEEP = 0x03,
-	AP_SLEEP = 0x04,
-	AP_IDLE = 0x05,
-	AP_RESET = 0x06
-};
-
-/**
- * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
- * @NO_TRANSITION: No power state transition
- * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
- * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
- * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
- * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
- *                          ApDeepSleep
- * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
- */
-enum ap_pwrst_trans {
-	NO_TRANSITION			= 0x00,
-	APEXECUTE_TO_APSLEEP		= 0x01,
-	APIDLE_TO_APSLEEP		= 0x02, /* To be removed */
-	PRCMU_AP_SLEEP			= 0x01,
-	APBOOT_TO_APEXECUTE		= 0x03,
-	APEXECUTE_TO_APDEEPSLEEP	= 0x04, /* To be removed */
-	PRCMU_AP_DEEP_SLEEP		= 0x04,
-	APEXECUTE_TO_APIDLE		= 0x05, /* To be removed */
-	PRCMU_AP_IDLE			= 0x05,
-	PRCMU_AP_DEEP_IDLE		= 0x07,
-};
-
-/**
- * enum ddr_pwrst - DDR power states definition
- * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
- * @DDR_PWR_STATE_ON:
- * @DDR_PWR_STATE_OFFLOWLAT:
- * @DDR_PWR_STATE_OFFHIGHLAT:
- */
-enum ddr_pwrst {
-	DDR_PWR_STATE_UNCHANGED     = 0x00,
-	DDR_PWR_STATE_ON            = 0x01,
-	DDR_PWR_STATE_OFFLOWLAT     = 0x02,
-	DDR_PWR_STATE_OFFHIGHLAT    = 0x03
-};
-
-/**
- * enum arm_opp - ARM OPP states definition
- * @ARM_OPP_INIT:
- * @ARM_NO_CHANGE: The ARM operating point is unchanged
- * @ARM_100_OPP: The new ARM operating point is arm100opp
- * @ARM_50_OPP: The new ARM operating point is arm50opp
- * @ARM_MAX_OPP: Operating point is "max" (more than 100)
- * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
- * @ARM_EXTCLK: The new ARM operating point is armExtClk
- */
-enum arm_opp {
-	ARM_OPP_INIT = 0x00,
-	ARM_NO_CHANGE = 0x01,
-	ARM_100_OPP = 0x02,
-	ARM_50_OPP = 0x03,
-	ARM_MAX_OPP = 0x04,
-	ARM_MAX_FREQ100OPP = 0x05,
-	ARM_EXTCLK = 0x07
-};
-
-/**
- * enum ape_opp - APE OPP states definition
- * @APE_OPP_INIT:
- * @APE_NO_CHANGE: The APE operating point is unchanged
- * @APE_100_OPP: The new APE operating point is ape100opp
- * @APE_50_OPP: 50%
- */
-enum ape_opp {
-	APE_OPP_INIT = 0x00,
-	APE_NO_CHANGE = 0x01,
-	APE_100_OPP = 0x02,
-	APE_50_OPP = 0x03
-};
-
-/**
- * enum hw_acc_state - State definition for hardware accelerator
- * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
- * @HW_OFF: The hardware accelerator must be switched off
- * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
- *               internal RAM in retention
- * @HW_ON: The hwa hardware accelerator hwa must be switched on
- *
- * NOTE! Deprecated, to be removed when all users switched over to use the
- * regulator API.
- */
-enum hw_acc_state {
-	HW_NO_CHANGE = 0x00,
-	HW_OFF = 0x01,
-	HW_OFF_RAMRET = 0x02,
-	HW_ON = 0x04
-};
-
-/**
- * enum  mbox_2_arm_stat - Status messages definition for mbox_arm
- * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
- *                    completed
- * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
- *              completed
- * @SLEEPOK: The apExecute to apSleep state transition has been completed
- * @IDLEOK: The apExecute to apIdle state transition has been completed
- * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
- * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
- * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
- * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
- *                       going
- * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
- *                       going
- * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
- *                         been completed
- * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
- * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
- * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
- *                     completed
- * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
- * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
- * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
- *                    completed
- * @INIT_STATUS: Status init
- */
-enum ap_pwrsttr_status {
-	BOOT_TO_EXECUTEOK = 0xFF,
-	DEEPSLEEPOK = 0xFE,
-	SLEEPOK = 0xFD,
-	IDLEOK = 0xFC,
-	SOFTRESETOK = 0xFB,
-	SOFTRESETGO = 0xFA,
-	BOOT_TO_EXECUTE = 0xF9,
-	EXECUTE_TO_DEEPSLEEP = 0xF8,
-	DEEPSLEEP_TO_EXECUTE = 0xF7,
-	DEEPSLEEP_TO_EXECUTEOK = 0xF6,
-	EXECUTE_TO_SLEEP = 0xF5,
-	SLEEP_TO_EXECUTE = 0xF4,
-	SLEEP_TO_EXECUTEOK = 0xF3,
-	EXECUTE_TO_IDLE = 0xF2,
-	IDLE_TO_EXECUTE = 0xF1,
-	IDLE_TO_EXECUTEOK = 0xF0,
-	RDYTODS_RETURNTOEXE    = 0xEF,
-	NORDYTODS_RETURNTOEXE  = 0xEE,
-	EXETOSLEEP_RETURNTOEXE = 0xED,
-	EXETOIDLE_RETURNTOEXE  = 0xEC,
-	INIT_STATUS = 0xEB,
-
-	/*error messages */
-	INITERROR                     = 0x00,
-	PLLARMLOCKP_ER                = 0x01,
-	PLLDDRLOCKP_ER                = 0x02,
-	PLLSOCLOCKP_ER                = 0x03,
-	PLLSOCK1LOCKP_ER              = 0x04,
-	ARMWFI_ER                     = 0x05,
-	SYSCLKOK_ER                   = 0x06,
-	I2C_NACK_DATA_ER              = 0x07,
-	BOOT_ER                       = 0x08,
-	I2C_STATUS_ALWAYS_1           = 0x0A,
-	I2C_NACK_REG_ADDR_ER          = 0x0B,
-	I2C_NACK_DATA0123_ER          = 0x1B,
-	I2C_NACK_ADDR_ER              = 0x1F,
-	CURAPPWRSTISNOT_BOOT          = 0x20,
-	CURAPPWRSTISNOT_EXECUTE       = 0x21,
-	CURAPPWRSTISNOT_SLEEPMODE     = 0x22,
-	CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
-	FIFO4500WUISNOT_WUPEVENT      = 0x24,
-	PLL32KLOCKP_ER                = 0x29,
-	DDRDEEPSLEEPOK_ER             = 0x2A,
-	ROMCODEREADY_ER               = 0x50,
-	WUPBEFOREDS                   = 0x51,
-	DDRCONFIG_ER                  = 0x52,
-	WUPBEFORESLEEP                = 0x53,
-	WUPBEFOREIDLE                 = 0x54
-};  /* earlier called as  mbox_2_arm_stat */
-
-/**
- * enum dvfs_stat - DVFS status messages definition
- * @DVFS_GO: A state transition DVFS is on going
- * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
- * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
- * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
- * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
- *                   NOCHGCLK
- * @DVFS_INITSTATUS: Value init
- */
-enum dvfs_stat {
-	DVFS_GO = 0xFF,
-	DVFS_ARM100OPPOK = 0xFE,
-	DVFS_ARM50OPPOK = 0xFD,
-	DVFS_ARMEXTCLKOK = 0xFC,
-	DVFS_NOCHGTCLKOK = 0xFB,
-	DVFS_INITSTATUS = 0x00
-};
-
-/**
- * enum sva_mmdsp_stat - SVA MMDSP status messages
- * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
- * @SVA_MMDSP_INIT: Status init
- */
-enum sva_mmdsp_stat {
-	SVA_MMDSP_GO = 0xFF,
-	SVA_MMDSP_INIT = 0x00
-};
-
-/**
- * enum sia_mmdsp_stat - SIA MMDSP status messages
- * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
- * @SIA_MMDSP_INIT: Status init
- */
-enum sia_mmdsp_stat {
-	SIA_MMDSP_GO = 0xFF,
-	SIA_MMDSP_INIT = 0x00
-};
-
-/**
- * enum  mbox_to_arm_err - Error messages definition
- * @INIT_ERR: Init value
- * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
- * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
- * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
- * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
- * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
- * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
- * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
- * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
- * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
- *          through I2C has not been correctly executed in the given time
- * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
- *             through I2C has not been correctly executed in the given time
- * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
- *                     I2C has not been correctly executed in the given time
- * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
- *             through I2C has not been correctly executed in the given time
- * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
- *                     I2C has not been correctly executed in the given time
- * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
- *             through I2C has not been correctly executed in the given time
- * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
- *                     I2C has not been correctly executed in the given time
- * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
- *                         has not been correctly executed in the given time
- * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
- *                             not been correctly executed in the given time
- * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
- *                             not been correctly executed in the given time
- * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
- *                     I2C has not been correctly executed in the given time
- * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
- *                     I2C has not been correctly executed in the given time
- * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
- *             through I2C has not been correctly executed in the given time
- * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
- *             ApBoot to ApExecute but the power current state is not Apboot
- * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
- *              transition from ApExecute to others power state but the
- *              power current state is not ApExecute
- * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
- *             but the power current state is not ApDeepSleep/ApSleep/ApIdle
- * @CURAPPWRSTISNOTCORRECTDBG:  Generated when wake up events are transmitted
- *              but the power current state is not correct
- * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
- *                    been correctly executed in the given time
- * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
- *                    been correctly executed in the given time
- * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
- *                    been correctly executed in the given time
- * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
- *                      been correctly executed in the given time
- * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
- *                    been correctly executed in the given time
- */
-enum mbox_to_arm_err {
-	INIT_ERR = 0x00,
-	PLLARMLOCKP_ERR = 0x01,
-	PLLDDRLOCKP_ERR = 0x02,
-	PLLSOC0LOCKP_ERR = 0x03,
-	PLLSOC1LOCKP_ERR = 0x04,
-	ARMWFI_ERR = 0x05,
-	SYSCLKOK_ERR = 0x06,
-	BOOT_ERR = 0x07,
-	ROMCODESAVECONTEXT = 0x08,
-	VARMHIGHSPEEDVALTO_ERR = 0x10,
-	VARMHIGHSPEEDACCESS_ERR = 0x11,
-	VARMLOWSPEEDVALTO_ERR = 0x12,
-	VARMLOWSPEEDACCESS_ERR = 0x13,
-	VARMRETENTIONVALTO_ERR = 0x14,
-	VARMRETENTIONACCESS_ERR = 0x15,
-	VAPEHIGHSPEEDVALTO_ERR = 0x16,
-	VSAFEHPVALTO_ERR = 0x17,
-	VMODSEL1VALTO_ERR = 0x18,
-	VMODSEL2VALTO_ERR = 0x19,
-	VARMOFFACCESS_ERR = 0x1A,
-	VAPEOFFACCESS_ERR = 0x1B,
-	VARMRETACCES_ERR = 0x1C,
-	CURAPPWRSTISNOTBOOT = 0x20,
-	CURAPPWRSTISNOTEXECUTE = 0x21,
-	CURAPPWRSTISNOTSLEEPMODE = 0x22,
-	CURAPPWRSTISNOTCORRECTDBG = 0x23,
-	ARMREGU1VALTO_ERR = 0x24,
-	ARMREGU2VALTO_ERR = 0x25,
-	VAPEREGUVALTO_ERR = 0x26,
-	VSMPS3REGUVALTO_ERR = 0x27,
-	VMODREGUVALTO_ERR = 0x28
-};
-
-enum hw_acc {
-	SVAMMDSP = 0,
-	SVAPIPE = 1,
-	SIAMMDSP = 2,
-	SIAPIPE = 3,
-	SGA = 4,
-	B2R2MCDE = 5,
-	ESRAM12 = 6,
-	ESRAM34 = 7,
-};
-
-enum cs_pwrmgt {
-	PWRDNCS0  = 0,
-	WKUPCS0   = 1,
-	PWRDNCS1  = 2,
-	WKUPCS1   = 3
-};
-
-/* Defs related to autonomous power management */
-
-/**
- * enum sia_sva_pwr_policy - Power policy
- * @NO_CHGT:	No change
- * @DSPOFF_HWPOFF:
- * @DSPOFFRAMRET_HWPOFF:
- * @DSPCLKOFF_HWPOFF:
- * @DSPCLKOFF_HWPCLKOFF:
- *
- */
-enum sia_sva_pwr_policy {
-	NO_CHGT			= 0x0,
-	DSPOFF_HWPOFF		= 0x1,
-	DSPOFFRAMRET_HWPOFF	= 0x2,
-	DSPCLKOFF_HWPOFF	= 0x3,
-	DSPCLKOFF_HWPCLKOFF	= 0x4,
-};
-
-/**
- * enum auto_enable - Auto Power enable
- * @AUTO_OFF:
- * @AUTO_ON:
- *
- */
-enum auto_enable {
-	AUTO_OFF	= 0x0,
-	AUTO_ON		= 0x1,
-};
-
-#endif /* __MACH_PRCMU_FW_DEFS_V1_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-qos.h b/arch/arm/mach-ux500/include/mach/prcmu-qos.h
new file mode 100644
index 00000000000..00dcab689de
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-qos.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) ST Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCMU QoS
+ */
+#ifndef __MACH_PRCMU_QOS_H
+#define __MACH_PRCMU_QOS_H
+
+#include <linux/notifier.h>
+
+/* PRCMU QoS APE OPP class */
+#define PRCMU_QOS_APE_OPP 1
+#define PRCMU_QOS_DDR_OPP 2
+#define PRCMU_QOS_DEFAULT_VALUE -1
+
+#ifdef CONFIG_UX500_SOC_DB8500
+
+unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
+void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
+void prcmu_qos_force_opp(int, s32);
+
+#else /* !CONFIG_UX500_SOC_DB8500 */
+
+static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
+{
+	return 0;
+}
+
+static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
+
+static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
+
+#endif /* CONFIG_UX500_SOC_DB8500 */
+
+#ifdef CONFIG_UX500_PRCMU_QOS_POWER
+
+int prcmu_qos_requirement(int pm_qos_class);
+int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
+int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
+void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
+int prcmu_qos_add_notifier(int prcmu_qos_class,
+			   struct notifier_block *notifier);
+int prcmu_qos_remove_notifier(int prcmu_qos_class,
+			      struct notifier_block *notifier);
+
+#else
+
+static inline int prcmu_qos_requirement(int prcmu_qos_class)
+{
+	return 0;
+}
+
+static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
+					    char *name, s32 value)
+{
+	return 0;
+}
+
+static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
+					       char *name, s32 new_value)
+{
+	return 0;
+}
+
+static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
+{
+}
+
+static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
+					 struct notifier_block *notifier)
+{
+	return 0;
+}
+static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
+					    struct notifier_block *notifier)
+{
+	return 0;
+}
+
+#endif
+
+#endif /* __MACH_PRCMU_QOS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
new file mode 100644
index 00000000000..bc9defd3086
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -0,0 +1,345 @@
+/*
+ * Copyright (C) ST Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * STE Ux500 PRCMU API
+ */
+#ifndef __MACH_PRCMU_H
+#define __MACH_PRCMU_H
+
+#include <linux/interrupt.h>
+#include <mach/prcmu-qos.h>
+
+/* PRCMU Wakeup defines */
+enum prcmu_wakeup_index {
+	PRCMU_WAKEUP_INDEX_RTC,
+	PRCMU_WAKEUP_INDEX_RTT0,
+	PRCMU_WAKEUP_INDEX_RTT1,
+	PRCMU_WAKEUP_INDEX_HSI0,
+	PRCMU_WAKEUP_INDEX_HSI1,
+	PRCMU_WAKEUP_INDEX_USB,
+	PRCMU_WAKEUP_INDEX_ABB,
+	PRCMU_WAKEUP_INDEX_ABB_FIFO,
+	PRCMU_WAKEUP_INDEX_ARM,
+	NUM_PRCMU_WAKEUP_INDICES
+};
+#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
+
+/* Low power states */
+#define PRCMU_AP_NO_CHANGE 0x00
+#define PRCMU_AP_SLEEP 0x01
+#define PRCMU_AP_DEEP_SLEEP 0x04
+#define PRCMU_AP_IDLE 0x05
+#define PRCMU_AP_DEEP_IDLE 0x07
+/* Legacy names */
+#define APEXECUTE_TO_APSLEEP PRCMU_AP_SLEEP
+
+/* EPOD (power domain) IDs */
+
+/*
+ * DB8500 EPODs
+ * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
+ * - EPOD_ID_SVAPIPE: power domain for SVA pipe
+ * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
+ * - EPOD_ID_SIAPIPE: power domain for SIA pipe
+ * - EPOD_ID_SGA: power domain for SGA
+ * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
+ * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
+ * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
+ * - NUM_EPOD_ID: number of power domains
+ *
+ * TODO: These should be prefixed.
+ */
+#define EPOD_ID_SVAMMDSP	0
+#define EPOD_ID_SVAPIPE		1
+#define EPOD_ID_SIAMMDSP	2
+#define EPOD_ID_SIAPIPE		3
+#define EPOD_ID_SGA		4
+#define EPOD_ID_B2R2_MCDE	5
+#define EPOD_ID_ESRAM12		6
+#define EPOD_ID_ESRAM34		7
+#define NUM_EPOD_ID		8
+
+/*
+ * DB5500 EPODs
+ */
+#define DB5500_EPOD_ID_BASE 0x0100
+#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
+#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
+#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
+#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
+#define DB5500_EPOD_ID_B2R2 (DB5500_EPOD_ID_BASE + 4)
+#define DB5500_EPOD_ID_MODEM (DB5500_EPOD_ID_BASE + 5)
+#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
+#define DB5500_NUM_EPOD_ID 7
+
+/*
+ * state definition for EPOD (power domain)
+ * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
+ * - EPOD_STATE_OFF: The EPOD is switched off
+ * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
+ *                         retention
+ * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
+ * - EPOD_STATE_ON: Same as above, but with clock enabled
+ */
+#define EPOD_STATE_NO_CHANGE	0x00
+#define EPOD_STATE_OFF		0x01
+#define EPOD_STATE_RAMRET	0x02
+#define EPOD_STATE_ON_CLK_OFF	0x03
+#define EPOD_STATE_ON		0x04
+
+/*
+ * CLKOUT sources
+ */
+#define PRCMU_CLKSRC_CLK38M		0x00
+#define PRCMU_CLKSRC_ACLK		0x01
+#define PRCMU_CLKSRC_SYSCLK		0x02
+#define PRCMU_CLKSRC_LCDCLK		0x03
+#define PRCMU_CLKSRC_SDMMCCLK		0x04
+#define PRCMU_CLKSRC_TVCLK		0x05
+#define PRCMU_CLKSRC_TIMCLK		0x06
+#define PRCMU_CLKSRC_CLK009		0x07
+/* These are only valid for CLKOUT1: */
+#define PRCMU_CLKSRC_SIAMMDSPCLK	0x40
+#define PRCMU_CLKSRC_I2CCLK		0x41
+#define PRCMU_CLKSRC_MSP02CLK		0x42
+#define PRCMU_CLKSRC_ARMPLL_OBSCLK	0x43
+#define PRCMU_CLKSRC_HSIRXCLK		0x44
+#define PRCMU_CLKSRC_HSITXCLK		0x45
+#define PRCMU_CLKSRC_ARMCLKFIX		0x46
+#define PRCMU_CLKSRC_HDMICLK		0x47
+
+/*
+ * Clock identifiers.
+ */
+enum prcmu_clock {
+	PRCMU_SGACLK,
+	PRCMU_UARTCLK,
+	PRCMU_MSP02CLK,
+	PRCMU_MSP1CLK,
+	PRCMU_I2CCLK,
+	PRCMU_SDMMCCLK,
+	PRCMU_SLIMCLK,
+	PRCMU_PER1CLK,
+	PRCMU_PER2CLK,
+	PRCMU_PER3CLK,
+	PRCMU_PER5CLK,
+	PRCMU_PER6CLK,
+	PRCMU_PER7CLK,
+	PRCMU_LCDCLK,
+	PRCMU_BMLCLK,
+	PRCMU_HSITXCLK,
+	PRCMU_HSIRXCLK,
+	PRCMU_HDMICLK,
+	PRCMU_APEATCLK,
+	PRCMU_APETRACECLK,
+	PRCMU_MCDECLK,
+	PRCMU_IPI2CCLK,
+	PRCMU_DSIALTCLK,
+	PRCMU_DMACLK,
+	PRCMU_B2R2CLK,
+	PRCMU_TVCLK,
+	PRCMU_SSPCLK,
+	PRCMU_RNGCLK,
+	PRCMU_UICCCLK,
+	PRCMU_NUM_REG_CLOCKS,
+	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
+	PRCMU_PLLSOC1,
+	PRCMU_TIMCLK,
+};
+
+/**
+ * enum ape_opp - APE OPP states definition
+ * @APE_OPP_INIT:
+ * @APE_NO_CHANGE: The APE operating point is unchanged
+ * @APE_100_OPP: The new APE operating point is ape100opp
+ * @APE_50_OPP: 50%
+ */
+enum ape_opp {
+	APE_OPP_INIT = 0x00,
+	APE_NO_CHANGE = 0x01,
+	APE_100_OPP = 0x02,
+	APE_50_OPP = 0x03
+};
+
+/**
+ * enum arm_opp - ARM OPP states definition
+ * @ARM_OPP_INIT:
+ * @ARM_NO_CHANGE: The ARM operating point is unchanged
+ * @ARM_100_OPP: The new ARM operating point is arm100opp
+ * @ARM_50_OPP: The new ARM operating point is arm50opp
+ * @ARM_MAX_OPP: Operating point is "max" (more than 100)
+ * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
+ * @ARM_EXTCLK: The new ARM operating point is armExtClk
+ */
+enum arm_opp {
+	ARM_OPP_INIT = 0x00,
+	ARM_NO_CHANGE = 0x01,
+	ARM_100_OPP = 0x02,
+	ARM_50_OPP = 0x03,
+	ARM_MAX_OPP = 0x04,
+	ARM_MAX_FREQ100OPP = 0x05,
+	ARM_EXTCLK = 0x07
+};
+
+/**
+ * enum ddr_opp - DDR OPP states definition
+ * @DDR_100_OPP: The new DDR operating point is ddr100opp
+ * @DDR_50_OPP: The new DDR operating point is ddr50opp
+ * @DDR_25_OPP: The new DDR operating point is ddr25opp
+ */
+enum ddr_opp {
+	DDR_100_OPP = 0x00,
+	DDR_50_OPP = 0x01,
+	DDR_25_OPP = 0x02,
+};
+
+#include <mach/prcmu-db8500.h>
+#include <mach/prcmu-db5500.h>
+
+#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
+
+void __init prcmu_early_init(void);
+
+int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
+
+int prcmu_set_epod(u16 epod_id, u8 epod_state);
+
+void prcmu_enable_wakeups(u32 wakeups);
+static inline void prcmu_disable_wakeups(void)
+{
+	prcmu_enable_wakeups(0);
+}
+
+int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
+int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+
+int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
+
+int prcmu_request_clock(u8 clock, bool enable);
+
+int prcmu_set_ape_opp(u8 opp);
+int prcmu_get_ape_opp(void);
+int prcmu_set_arm_opp(u8 opp);
+int prcmu_get_arm_opp(void);
+int prcmu_set_ddr_opp(u8 opp);
+int prcmu_get_ddr_opp(void);
+
+void prcmu_system_reset(u16 reset_code);
+u16 prcmu_get_reset_code(void);
+
+void prcmu_ac_wake_req(void);
+void prcmu_ac_sleep_req(void);
+void prcmu_modem_reset(void);
+bool prcmu_is_ac_wake_requested(void);
+
+int prcmu_set_display_clocks(void);
+int prcmu_disable_dsipll(void);
+int prcmu_enable_dsipll(void);
+
+#else
+
+static inline void __init prcmu_early_init(void) {}
+
+static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+	bool keep_ap_pll)
+{
+	return 0;
+}
+
+static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
+{
+	return 0;
+}
+
+static inline void prcmu_enable_wakeups(u32 wakeups) {}
+
+static inline void prcmu_disable_wakeups(void) {}
+
+static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+	return -ENOSYS;
+}
+
+static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+	return -ENOSYS;
+}
+
+static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
+{
+	return 0;
+}
+
+static inline int prcmu_request_clock(u8 clock, bool enable)
+{
+	return 0;
+}
+
+static inline int prcmu_set_ape_opp(u8 opp)
+{
+	return 0;
+}
+
+static inline int prcmu_get_ape_opp(void)
+{
+	return APE_100_OPP;
+}
+
+static inline int prcmu_set_arm_opp(u8 opp)
+{
+	return 0;
+}
+
+static inline int prcmu_get_arm_opp(void)
+{
+	return ARM_100_OPP;
+}
+
+static inline int prcmu_set_ddr_opp(u8 opp)
+{
+	return 0;
+}
+
+static inline int prcmu_get_ddr_opp(void)
+{
+	return DDR_100_OPP;
+}
+
+static inline void prcmu_system_reset(u16 reset_code) {}
+
+static inline u16 prcmu_get_reset_code(void)
+{
+	return 0;
+}
+
+static inline void prcmu_ac_wake_req(void) {}
+
+static inline void prcmu_ac_sleep_req(void) {}
+
+static inline void prcmu_modem_reset(void) {}
+
+static inline bool prcmu_is_ac_wake_requested(void)
+{
+	return false;
+}
+
+static inline int prcmu_set_display_clocks(void)
+{
+	return 0;
+}
+
+static inline int prcmu_disable_dsipll(void)
+{
+	return 0;
+}
+
+static inline int prcmu_enable_dsipll(void)
+{
+	return 0;
+}
+
+#endif
+
+#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/system.h b/arch/arm/mach-ux500/include/mach/system.h
index ec056d9198c..89699238681 100644
--- a/arch/arm/mach-ux500/include/mach/system.h
+++ b/arch/arm/mach-ux500/include/mach/system.h
@@ -8,7 +8,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <mach/reboot_reasons.h>
 
 static inline void arch_idle(void)
diff --git a/arch/arm/mach-ux500/pm/cpufreq-db8500.c b/arch/arm/mach-ux500/pm/cpufreq-db8500.c
index 0d7173eb4dd..9b2f2b15e01 100644
--- a/arch/arm/mach-ux500/pm/cpufreq-db8500.c
+++ b/arch/arm/mach-ux500/pm/cpufreq-db8500.c
@@ -7,7 +7,7 @@
 #include <linux/kernel.h>
 #include <linux/cpufreq.h>
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #include "cpufreq.h"
 
diff --git a/arch/arm/mach-ux500/pm/cpufreq.c b/arch/arm/mach-ux500/pm/cpufreq.c
index 4583372094a..0c28eb79906 100644
--- a/arch/arm/mach-ux500/pm/cpufreq.c
+++ b/arch/arm/mach-ux500/pm/cpufreq.c
@@ -14,7 +14,7 @@
 #include <linux/slab.h>
 
 #include <mach/hardware.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <mach/prcmu-regs.h>
 
 static struct cpufreq_frequency_table *freq_table;
diff --git a/arch/arm/mach-ux500/pm/cpuidle.c b/arch/arm/mach-ux500/pm/cpuidle.c
index 522cf4b39ee..7c8bb5bf0e8 100644
--- a/arch/arm/mach-ux500/pm/cpuidle.c
+++ b/arch/arm/mach-ux500/pm/cpuidle.c
@@ -18,7 +18,7 @@
 
 #include <linux/gpio.h>
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #include "cpuidle.h"
 #include "cpuidle_dbg.h"
@@ -65,7 +65,7 @@ static struct cstate cstates[] = {
 		.ARM_PLL = ARM_PLL_ON,
 		.UL_PLL = UL_PLL_ON,
 		.ESRAM = ESRAM_RET,
-		.pwrst = NO_TRANSITION,
+		.pwrst = PRCMU_AP_NO_CHANGE,
 		.state = CI_RUNNING,
 		.desc = "Running                ",
 	},
@@ -80,7 +80,7 @@ static struct cstate cstates[] = {
 		.ARM_PLL = ARM_PLL_ON,
 		.UL_PLL = UL_PLL_ON,
 		.ESRAM = ESRAM_RET,
-		.pwrst = NO_TRANSITION,
+		.pwrst = PRCMU_AP_NO_CHANGE,
 		.flags = CPUIDLE_FLAG_TIME_VALID,
 		.state = CI_WFI,
 		.desc = "Wait for interrupt     ",
diff --git a/arch/arm/mach-ux500/pm/cpuidle.h b/arch/arm/mach-ux500/pm/cpuidle.h
index 618e0f969e5..f15338aa48b 100644
--- a/arch/arm/mach-ux500/pm/cpuidle.h
+++ b/arch/arm/mach-ux500/pm/cpuidle.h
@@ -11,8 +11,6 @@
 
 #include <linux/cpuidle.h>
 
-#include <mach/prcmu-fw-defs_v1.h>
-
 enum ARM {
 	ARM_OFF,
 	ARM_RET,
@@ -62,7 +60,7 @@ struct cstate {
 	u32 power_usage;
 	u32 threshold;
 	u32 flags;
-	enum ap_pwrst_trans pwrst;
+	u8 pwrst;
 
 	/* Only used for debugging purpose */
 	enum ci_pwrst state;
diff --git a/arch/arm/mach-ux500/pm/suspend.c b/arch/arm/mach-ux500/pm/suspend.c
index 46a8ed0ccd8..9f4573b42e1 100644
--- a/arch/arm/mach-ux500/pm/suspend.c
+++ b/arch/arm/mach-ux500/pm/suspend.c
@@ -15,7 +15,7 @@
 #include <linux/delay.h>
 #include <linux/regulator/ab8500-debug.h>
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <mach/prcmu-regs.h>
 
 #include "context.h"
diff --git a/arch/arm/mach-ux500/prcmu-db5500.c b/arch/arm/mach-ux500/prcmu-db5500.c
index 96dc23c32dd..7e7b02d2e8e 100644
--- a/arch/arm/mach-ux500/prcmu-db5500.c
+++ b/arch/arm/mach-ux500/prcmu-db5500.c
@@ -23,12 +23,10 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/prcmu-db5500.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <mach/db5500-regs.h>
 
 #include "prcmu-regs-db5500.h"
-#include "prcmu-db5500.h"
 
 #define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
 #define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
diff --git a/arch/arm/mach-ux500/prcmu-db5500.h b/arch/arm/mach-ux500/prcmu-db5500.h
deleted file mode 100644
index 713bd0d858d..00000000000
--- a/arch/arm/mach-ux500/prcmu-db5500.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2011
- *
- * License terms: GNU General Public License, version 2
- */
-
-#ifndef __MACH_PRCMU_DB4500_H
-#define __MACH_PRCMU_DB4500_H
-
-/*
- * Clock identifiers.
- */
-enum db5500_prcmu_clock {
-	DB5500_PRCMU_SGACLK,
-	DB5500_PRCMU_UARTCLK,
-	DB5500_PRCMU_MSP02CLK,
-	DB5500_PRCMU_I2CCLK,
-	DB5500_PRCMU_SDMMCCLK,
-	DB5500_PRCMU_PER1CLK,
-	DB5500_PRCMU_PER2CLK,
-	DB5500_PRCMU_PER3CLK,
-	DB5500_PRCMU_PER5CLK,
-	DB5500_PRCMU_PER6CLK,
-	DB5500_PRCMU_PWMCLK,
-	DB5500_PRCMU_IRDACLK,
-	DB5500_PRCMU_IRRCCLK,
-	DB5500_PRCMU_HDMICLK,
-	DB5500_PRCMU_APEATCLK,
-	DB5500_PRCMU_APETRACECLK,
-	DB5500_PRCMU_MCDECLK,
-	DB5500_PRCMU_DSIALTCLK,
-	DB5500_PRCMU_DMACLK,
-	DB5500_PRCMU_B2R2CLK,
-	DB5500_PRCMU_TVCLK,
-	DB5500_PRCMU_RNGCLK,
-	DB5500_PRCMU_NUM_REG_CLOCKS,
-	DB5500_PRCMU_SYSCLK = DB5500_PRCMU_NUM_REG_CLOCKS,
-	DB5500_PRCMU_TIMCLK,
-};
-
-extern int db5500_prcmu_request_clock(u8 clock, bool enable);
-
-#endif
diff --git a/arch/arm/mach-ux500/prcmu-db8500.c b/arch/arm/mach-ux500/prcmu-db8500.c
index f335fe5a76c..00e80e0d474 100644
--- a/arch/arm/mach-ux500/prcmu-db8500.c
+++ b/arch/arm/mach-ux500/prcmu-db8500.c
@@ -37,8 +37,7 @@
 #include <mach/irqs.h>
 #include "prcmu-regs-db8500.h"
 #include "prcmu-debug.h"
-#include <mach/prcmu-fw-api.h>
-#include <mach/prcmu-fw-defs_v1.h>
+#include <mach/prcmu.h>
 #include <mach/db8500-regs.h>
 #include <mach/id.h>
 
@@ -1345,7 +1344,7 @@ static int request_sysclk(bool enable)
 	while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
 		cpu_relax();
 
-	writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
+	writeb((enable ? 1 : 0), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
 
 	writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
 	writel(MBOX_BIT(3), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
diff --git a/arch/arm/mach-ux500/prcmu-debug.c b/arch/arm/mach-ux500/prcmu-debug.c
index 98c4cff30e5..e41a93ccb84 100644
--- a/arch/arm/mach-ux500/prcmu-debug.c
+++ b/arch/arm/mach-ux500/prcmu-debug.c
@@ -16,7 +16,7 @@
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 enum ape_opp_debug {
 	APE_50_OPP_DEBUG,
diff --git a/arch/arm/mach-ux500/prcmu-qos-power.c b/arch/arm/mach-ux500/prcmu-qos-power.c
index 0d221e405e2..050bcf2f7ad 100644
--- a/arch/arm/mach-ux500/prcmu-qos-power.c
+++ b/arch/arm/mach-ux500/prcmu-qos-power.c
@@ -22,7 +22,7 @@
 #include <linux/cpufreq.h>
 
 #include "prcmu-debug.h"
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #define ARM_THRESHOLD_FREQ (400000)
 
diff --git a/arch/arm/mach-ux500/regulator-db8500.c b/arch/arm/mach-ux500/regulator-db8500.c
index f08093687d8..a9026c9b686 100644
--- a/arch/arm/mach-ux500/regulator-db8500.c
+++ b/arch/arm/mach-ux500/regulator-db8500.c
@@ -12,7 +12,7 @@
 #include <linux/regulator/driver.h>
 #include <linux/regulator/machine.h>
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #include "regulator-ux500.h"
 #include "regulator-db8500.h"
diff --git a/arch/arm/mach-ux500/regulator-u5500.c b/arch/arm/mach-ux500/regulator-u5500.c
index bd988c7c109..513a7763dbc 100644
--- a/arch/arm/mach-ux500/regulator-u5500.c
+++ b/arch/arm/mach-ux500/regulator-u5500.c
@@ -11,7 +11,7 @@
 #include <linux/regulator/driver.h>
 #include <linux/regulator/machine.h>
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #include "regulator-ux500.h"
 #include "regulator-u5500.h"
diff --git a/arch/arm/mach-ux500/regulator-ux500.c b/arch/arm/mach-ux500/regulator-ux500.c
index 6bd3a0e6d39..91b81896cab 100644
--- a/arch/arm/mach-ux500/regulator-ux500.c
+++ b/arch/arm/mach-ux500/regulator-ux500.c
@@ -18,7 +18,7 @@
 
 #include "regulator-ux500.h"
 
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 /*
  * power state reference count
diff --git a/drivers/hwmon/db8500.c b/drivers/hwmon/db8500.c
index b9b4312b8c1..c08ab033ada 100755
--- a/drivers/hwmon/db8500.c
+++ b/drivers/hwmon/db8500.c
@@ -13,7 +13,7 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/platform_device.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <linux/hwmon.h>
 #include <linux/sysfs.h>
 #include <linux/hwmon-sysfs.h>
diff --git a/drivers/mfd/ab8500-i2c.c b/drivers/mfd/ab8500-i2c.c
index bdfbdb5a558..5d44b82d1c0 100644
--- a/drivers/mfd/ab8500-i2c.c
+++ b/drivers/mfd/ab8500-i2c.c
@@ -14,6 +14,7 @@
 #include <linux/mfd/db8500-prcmu.h>
 #include <mach/prcmu-fw-api.h>
 
+
 static int ab8500_i2c_write(struct ab8500 *ab8500, u16 addr, u8 data)
 {
 	int ret;
diff --git a/drivers/misc/i2s/msp_i2s.c b/drivers/misc/i2s/msp_i2s.c
index 5645e980c93..343a502c68e 100644
--- a/drivers/misc/i2s/msp_i2s.c
+++ b/drivers/misc/i2s/msp_i2s.c
@@ -24,7 +24,7 @@
 #include <linux/pfn.h>
 
 #include <linux/regulator/consumer.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <mach/hardware.h>
 #include <asm/io.h>
 #include <asm/delay.h>
diff --git a/drivers/misc/shrm/shrm_protocol.c b/drivers/misc/shrm/shrm_protocol.c
index 0598c62812f..567c9b93d5f 100644
--- a/drivers/misc/shrm/shrm_protocol.c
+++ b/drivers/misc/shrm/shrm_protocol.c
@@ -16,7 +16,7 @@
 #include <mach/shrm_driver.h>
 #include <mach/shrm_private.h>
 #include <mach/shrm_net.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 #include <mach/prcmu-regs.h>
 #include <mach/suspend.h>
 #include <mach/reboot_reasons.h>
diff --git a/drivers/usb/otg/ab8500-usb.c b/drivers/usb/otg/ab8500-usb.c
index cfb6474d07c..e69c9988ea9 100644
--- a/drivers/usb/otg/ab8500-usb.c
+++ b/drivers/usb/otg/ab8500-usb.c
@@ -34,7 +34,7 @@
 #include <linux/mfd/abx500.h>
 #include <linux/mfd/ab8500.h>
 #include <linux/regulator/consumer.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #define AB8500_MAIN_WD_CTRL_REG 0x01
 #define AB8500_USB_LINE_STAT_REG 0x80
diff --git a/drivers/video/av8100/av8100.c b/drivers/video/av8100/av8100.c
index c3733c0ea40..a5e2bf4e731 100644
--- a/drivers/video/av8100/av8100.c
+++ b/drivers/video/av8100/av8100.c
@@ -27,7 +27,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/regulator/consumer.h>
-#include <mach/prcmu-fw-api.h>
+#include <mach/prcmu.h>
 
 #include "av8100_regs.h"
 #include <video/av8100.h>