diff options
author | Philippe Langlais <philippe.langlais@linaro.org> | 2011-07-06 13:49:55 +0200 |
---|---|---|
committer | Robert Marklund <robert.marklund@stericsson.com> | 2011-10-05 12:17:02 +0200 |
commit | fda2ad8cf563d623c8b987e3aab2d048d7a42c09 (patch) | |
tree | 86f11387b1e7318f902e37377c1ebc06ca221f52 | |
parent | 22f92b5b79d751749d2fb1e5427afba36a8abd94 (diff) |
mach-ux500: Fix PRCMU support on U5500 platforms for 3.0
Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org>
-rw-r--r-- | arch/arm/mach-ux500/board-u5500-pins.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-ux500/clock-db5500.c | 12 | ||||
-rw-r--r-- | arch/arm/mach-ux500/devices-db5500.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/prcmu-regs.h | 16 | ||||
-rw-r--r-- | arch/arm/mach-ux500/include/mach/prcmu.h | 46 | ||||
-rw-r--r-- | drivers/mfd/db5500-prcmu.c | 41 | ||||
-rw-r--r-- | drivers/mfd/db8500-prcmu.c | 16 | ||||
-rw-r--r-- | include/linux/mfd/db5500-prcmu.h | 45 | ||||
-rw-r--r-- | include/linux/mfd/db8500-prcmu.h | 46 |
9 files changed, 156 insertions, 70 deletions
diff --git a/arch/arm/mach-ux500/board-u5500-pins.c b/arch/arm/mach-ux500/board-u5500-pins.c index 18cc60796bb..f218c19cda1 100644 --- a/arch/arm/mach-ux500/board-u5500-pins.c +++ b/arch/arm/mach-ux500/board-u5500-pins.c @@ -7,8 +7,8 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/gpio.h> +#include <linux/gpio/nomadik.h> #include <plat/pincfg.h> -#include <plat/gpio.h> #include "pins-db5500.h" #include "pins.h" diff --git a/arch/arm/mach-ux500/clock-db5500.c b/arch/arm/mach-ux500/clock-db5500.c index 93f65e5cc79..ee2ea8033bd 100644 --- a/arch/arm/mach-ux500/clock-db5500.c +++ b/arch/arm/mach-ux500/clock-db5500.c @@ -15,7 +15,7 @@ #include <linux/mutex.h> #include <linux/debugfs.h> #include <linux/module.h> -#include <linux/gpio.h> +#include <linux/gpio/nomadik.h> #include <linux/mfd/ab8500/sysctrl.h> #include <linux/workqueue.h> #include <linux/regulator/consumer.h> @@ -25,10 +25,10 @@ #include <mach/hardware.h> #include <mach/prcmu.h> +#include <mach/prcmu-regs.h> #include "clock.h" #include "pins-db5500.h" -#include "prcmu-regs-db5500.h" static DEFINE_MUTEX(sysclk_mutex); static DEFINE_MUTEX(pll_mutex); @@ -206,12 +206,12 @@ static pin_cfg_t clkout1_pins[] = { static int clkout0_enable(struct clk *clk) { - unsigned int val = readl(_PRCMU_BASE + PRCM_CLKOCR); + unsigned int val = readl(PRCM_CLKOCR); val &= ~PRCM_CLKOCR_CLKOUT0_MASK; val |= PRCM_CLKOCR_CLKOUT0_REF_CLK; - writel(val, _PRCMU_BASE + PRCM_CLKOCR); + writel(val, PRCM_CLKOCR); return nmk_config_pins(clkout0_pins, ARRAY_SIZE(clkout0_pins)); } @@ -229,12 +229,12 @@ static void clkout0_disable(struct clk *clk) static int clkout1_enable(struct clk *clk) { - unsigned int val = readl(_PRCMU_BASE + PRCM_CLKOCR); + unsigned int val = readl(PRCM_CLKOCR); val &= ~PRCM_CLKOCR_CLKOUT1_MASK; val |= PRCM_CLKOCR_CLKOUT1_REF_CLK; - writel(val, _PRCMU_BASE + PRCM_CLKOCR); + writel(val, PRCM_CLKOCR); return nmk_config_pins(clkout1_pins, ARRAY_SIZE(clkout0_pins)); } diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c index 1a636722f29..aa6389a2c20 100644 --- a/arch/arm/mach-ux500/devices-db5500.c +++ b/arch/arm/mach-ux500/devices-db5500.c @@ -12,7 +12,7 @@ #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/platform_device.h> -#include <linux/gpio.h> +#include <linux/gpio/nomadik.h> #include <mach/hardware.h> #include <mach/devices.h> diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h index 121a5178f67..ec4663046e3 100644 --- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h +++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h @@ -17,10 +17,11 @@ #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end)) +#define PRCM_SVACLK_MGT_OFF 0x008 +#define PRCM_SIACLK_MGT_OFF 0x00C #define PRCM_SGACLK_MGT_OFF 0x014 #define PRCM_UARTCLK_MGT_OFF 0x018 #define PRCM_MSP02CLK_MGT_OFF 0x01C -#define PRCM_MSP1CLK_MGT_OFF 0x288 #define PRCM_I2CCLK_MGT_OFF 0x020 #define PRCM_SDMMCCLK_MGT_OFF 0x024 #define PRCM_SLIMCLK_MGT_OFF 0x028 @@ -30,6 +31,9 @@ #define PRCM_PER5CLK_MGT_OFF 0x038 #define PRCM_PER6CLK_MGT_OFF 0x03C #define PRCM_PER7CLK_MGT_OFF 0x040 +#define PRCM_PWMCLK_MGT_OFF 0x044 /* for DB5500 */ +#define PRCM_IRDACLK_MGT_OFF 0x048 /* for DB5500 */ +#define PRCM_IRRCCLK_MGT_OFF 0x04C /* for DB5500 */ #define PRCM_LCDCLK_MGT_OFF 0x044 #define PRCM_BMLCLK_MGT_OFF 0x04C #define PRCM_HSITXCLK_MGT_OFF 0x050 @@ -47,6 +51,7 @@ #define PRCM_SSPCLK_MGT_OFF 0x280 #define PRCM_RNGCLK_MGT_OFF 0x284 #define PRCM_UICCCLK_MGT_OFF 0x27C +#define PRCM_MSP1CLK_MGT_OFF 0x288 #define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118) #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f @@ -134,7 +139,12 @@ #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) #define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) #define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) + #define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC) +#define PRCM_CLKOCR_CLKOUT0_REF_CLK (1 << 0) +#define PRCM_CLKOCR_CLKOUT0_MASK BITS(0, 13) +#define PRCM_CLKOCR_CLKOUT1_REF_CLK (1 << 16) +#define PRCM_CLKOCR_CLKOUT1_MASK BITS(16, 29) /* ePOD and memory power signal control registers */ #define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410) @@ -179,4 +189,8 @@ #define PRCM_CGATING_BYPASS (_PRCMU_BASE + 0x134) #define PRCM_CGATING_BYPASS_ICN2 BIT(6) +/* Miscellaneous unit registers */ +#define PRCM_RESOUTN_SET (_PRCMU_BASE + 0x214) +#define PRCM_RESOUTN_CLR (_PRCMU_BASE + 0x218) + #endif /* __MACH_PRCMU__REGS_H */ diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h index 71d9dee80ce..41f68f0f087 100644 --- a/arch/arm/mach-ux500/include/mach/prcmu.h +++ b/arch/arm/mach-ux500/include/mach/prcmu.h @@ -10,6 +10,7 @@ #include <linux/interrupt.h> #include <linux/notifier.h> +#include <asm/mach-types.h> /* PRCMU Wakeup defines */ enum prcmu_wakeup_index { @@ -198,11 +199,33 @@ enum ddr_opp { void __init prcmu_early_init(void); -int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); +static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) +{ + if (machine_is_u5500()) + return db5500_prcmu_set_power_state(state, keep_ulp_clk, + keep_ap_pll); + else + return db8500_prcmu_set_power_state(state, keep_ulp_clk, + keep_ap_pll); +} -int prcmu_set_epod(u16 epod_id, u8 epod_state); +static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) +{ + if (machine_is_u5500()) + return db5500_prcmu_set_epod(epod_id, epod_state); + else + return db8500_prcmu_set_epod(epod_id, epod_state); +} + +static inline void prcmu_enable_wakeups(u32 wakeups) +{ + if (machine_is_u5500()) + db5500_prcmu_enable_wakeups(wakeups); + else + db8500_prcmu_enable_wakeups(wakeups); +} -void prcmu_enable_wakeups(u32 wakeups); static inline void prcmu_disable_wakeups(void) { prcmu_enable_wakeups(0); @@ -213,7 +236,13 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); int prcmu_config_clkout(u8 clkout, u8 source, u8 div); -int prcmu_request_clock(u8 clock, bool enable); +static inline int prcmu_request_clock(u8 clock, bool enable) +{ + if (machine_is_u5500()) + return db5500_prcmu_request_clock(clock, enable); + else + return db8500_prcmu_request_clock(clock, enable); +} int prcmu_set_ape_opp(u8 opp); int prcmu_get_ape_opp(void); @@ -222,7 +251,14 @@ int prcmu_get_arm_opp(void); int prcmu_set_ddr_opp(u8 opp); int prcmu_get_ddr_opp(void); -void prcmu_system_reset(u16 reset_code); +static inline void prcmu_system_reset(u16 reset_code) +{ + if (machine_is_u5500()) + return db5500_prcmu_system_reset(reset_code); + else + return db8500_prcmu_system_reset(reset_code); +} + u16 prcmu_get_reset_code(void); void prcmu_ac_wake_req(void); diff --git a/drivers/mfd/db5500-prcmu.c b/drivers/mfd/db5500-prcmu.c index 9cd9da40d87..7bbd34c04ad 100644 --- a/drivers/mfd/db5500-prcmu.c +++ b/drivers/mfd/db5500-prcmu.c @@ -24,7 +24,7 @@ #include <mach/irqs.h> #include <mach/prcmu.h> #include <mach/db5500-regs.h> -#include "db5500-prcmu-regs.h" +#include <mach/prcmu-regs.h> #define _PRCM_MB_HEADER (tcdm_base + 0xFE8) #define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0) @@ -245,7 +245,7 @@ static int request_timclk(bool enable) if (!enable) val |= PRCM_TCR_STOP_TIMERS; - writel(val, (_PRCMU_BASE + PRCM_TCR)); + writel(val, PRCM_TCR); return 0; } @@ -260,7 +260,7 @@ static int request_reg_clock(u8 clock, bool enable) spin_lock_irqsave(&clk_mgt_lock, flags); /* Grab the HW semaphore. */ - while ((readl(_PRCMU_BASE + PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) + while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0) cpu_relax(); val = readl(_PRCMU_BASE + clk_mgt[clock].offset); @@ -273,7 +273,7 @@ static int request_reg_clock(u8 clock, bool enable) writel(val, (_PRCMU_BASE + clk_mgt[clock].offset)); /* Release the HW semaphore. */ - writel(0, (_PRCMU_BASE + PRCM_SEM)); + writel(0, PRCM_SEM); spin_unlock_irqrestore(&clk_mgt_lock, flags); @@ -295,7 +295,7 @@ static int request_pll(u8 pll, bool enable) BUG_ON(pll >= DB5500_NUM_PLL_ID); mutex_lock(&mb2_transfer.lock); - while (readl(PRCM_MBOX_CPU_VAL & MBOX_BIT(2)) + while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2)) cpu_relax(); mb2_transfer.req.pll_states[pll] = enable; @@ -325,7 +325,7 @@ unlock_and_return: return r; } -void prcmu_enable_wakeups(u32 wakeups) +void db5500_prcmu_enable_wakeups(u32 wakeups) { } @@ -337,7 +337,7 @@ void prcmu_enable_wakeups(u32 wakeups) * This function should only be used by the clock implementation. * Do not use it from any other place! */ -int prcmu_request_clock(u8 clock, bool enable) +int db5500_prcmu_request_clock(u8 clock, bool enable) { if (clock < PRCMU_NUM_REG_CLOCKS) return request_reg_clock(clock, enable); @@ -439,11 +439,8 @@ int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) int prcmu_resetout(u8 resoutn, u8 state) { - int offset; int pin = -1; - offset = state > 0 ? PRCM_RESOUTN_SET_OFFSET : PRCM_RESOUTN_CLR_OFFSET; - switch (resoutn) { case 0: pin = PRCMU_RESOUTN0_PIN; @@ -458,7 +455,7 @@ int prcmu_resetout(u8 resoutn, u8 state) } if (pin > 0) - writel(pin, _PRCMU_BASE + offset); + writel(pin, state > 0 ? PRCM_RESOUTN_SET : PRCM_RESOUTN_CLR); else return -EINVAL; @@ -529,7 +526,7 @@ static void ack_dbb_wakeup(void) spin_unlock_irqrestore(&mb0_transfer.lock, flags); } -int prcmu_set_epod(u16 epod_id, u8 epod_state) +int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state) { int r = 0; bool ram_retention = false; @@ -616,13 +613,13 @@ static bool read_mailbox_0(void) r = false; break; } - writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR); return r; } static bool read_mailbox_1(void) { - writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR); return false; } @@ -643,25 +640,25 @@ static bool read_mailbox_2(void) mb2_transfer.ack.status = readb(PRCM_ACK_MB2_PLL_STATUS); break; default: - writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); pr_err("prcmu: Wrong ACK received for MB2 request \n"); return false; break; } - writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR); complete(&mb2_transfer.work); return false; } static bool read_mailbox_3(void) { - writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR); return false; } static bool read_mailbox_4(void) { - writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR); return false; } @@ -682,19 +679,19 @@ static bool read_mailbox_5(void) print_unknown_header_warning(5, header); break; } - writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR); return false; } static bool read_mailbox_6(void) { - writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR); return false; } static bool read_mailbox_7(void) { - writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR); + writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR); return false; } @@ -758,7 +755,7 @@ int __init db5500_prcmu_init(void) return -ENODEV; /* Clean up the mailbox interrupts after pre-kernel code. */ - writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLEAR); + writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR); r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler, prcmu_irq_thread_fn, 0, "prcmu", NULL); diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index f018c3fa604..5a1283d1a83 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -754,7 +754,7 @@ unlock_and_return: return r; } -int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) +int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) { unsigned long flags; @@ -811,7 +811,7 @@ static void config_wakeups(void) last_abb_events = abb_events; } -void prcmu_enable_wakeups(u32 wakeups) +void db8500_prcmu_enable_wakeups(u32 wakeups) { unsigned long flags; u32 bits; @@ -1198,14 +1198,14 @@ out: EXPORT_SYMBOL(prcmu_set_hwacc); /** - * prcmu_set_epod - set the state of a EPOD (power domain) + * db8500_prcmu_set_epod - set the state of a EPOD (power domain) * @epod_id: The EPOD to set * @epod_state: The new EPOD state * * This function sets the state of a EPOD (power domain). It may not be called * from interrupt context. */ -int prcmu_set_epod(u16 epod_id, u8 epod_state) +int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) { int r = 0; bool ram_retention = false; @@ -1415,14 +1415,14 @@ static int request_sga_clock(u8 clock, bool enable) } /** - * prcmu_request_clock() - Request for a clock to be enabled or disabled. + * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled. * @clock: The clock for which the request is made. * @enable: Whether the clock should be enabled (true) or disabled (false). * * This function should only be used by the clock implementation. * Do not use it from any other place! */ -int prcmu_request_clock(u8 clock, bool enable) +int db8500_prcmu_request_clock(u8 clock, bool enable) { if (clock == PRCMU_SGACLK) return request_sga_clock(clock, enable); @@ -1719,12 +1719,12 @@ bool prcmu_is_ac_wake_requested(void) } /** - * prcmu_system_reset - System reset + * db8500_prcmu_system_reset - System reset * * Saves the reset reason code and then sets the APE_SOFTRST register which * fires interrupt to fw */ -void prcmu_system_reset(u16 reset_code) +void db8500_prcmu_system_reset(u16 reset_code) { writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON)); writel(1, PRCM_APE_SOFTRST); diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h index 0d26f72230e..5be46a7157b 100644 --- a/include/linux/mfd/db5500-prcmu.h +++ b/include/linux/mfd/db5500-prcmu.h @@ -11,27 +11,28 @@ #ifdef CONFIG_UX500_SOC_DB5500 void db5500_prcmu_early_init(void); - +int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state); int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); +void db5500_prcmu_enable_wakeups(u32 wakeups); int db5500_prcmu_request_clock(u8 clock, bool enable); int prcmu_resetout(u8 resoutn, u8 state); -static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, +static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll) { return 0; } -static inline void prcmu_system_reset(u16 reset_code) {} +static inline void db5500_prcmu_system_reset(u16 reset_code) {} #else /* !CONFIG_UX500_SOC_DB5500 */ -static inline void db5500_prcmu_early_init(void) -{ -} +static inline void db5500_prcmu_early_init(void) {} + +static inline void db5500_prcmu_system_reset(u16 reset_code) {} static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) { @@ -43,6 +44,38 @@ static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) return -ENOSYS; } +static inline int db5500_prcmu_request_clock(u8 clock, bool enable) +{ + return 0; +} + + + return 0; +} + +static inline int db5500_prcmu_enable_dsipll(void) +{ + return 0; +} + +static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state) +{ + return 0; +} + +static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {} + +static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state) +{ + return 0; +} + +static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) +{ + return 0; +} + static inline int prcmu_resetout(u8 resoutn, u8 state) { return 0; diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h index b07b8159195..a03b51e991a 100644 --- a/include/linux/mfd/db8500-prcmu.h +++ b/include/linux/mfd/db8500-prcmu.h @@ -527,8 +527,6 @@ static inline void __init prcmu_early_init(void) {} int prcmu_set_rc_a2p(enum romcode_write); enum romcode_read prcmu_get_rc_p2a(void); enum ap_pwrst prcmu_get_xp70_current_state(void); -int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); -void prcmu_enable_wakeups(u32 wakeups); void prcmu_config_abb_event_readout(u32 abb_events); void prcmu_get_abb_event_buffer(void __iomem **buf); int prcmu_set_arm_opp(u8 opp); @@ -545,13 +543,11 @@ unsigned long prcmu_qos_get_cpufreq_opp_delay(void); void prcmu_qos_set_cpufreq_opp_delay(unsigned long); /* NOTE! Use regulator framework instead */ int prcmu_set_hwacc(u16 hw_acc_dev, u8 state); -int prcmu_set_epod(u16 epod_id, u8 epod_state); void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, struct prcmu_auto_pm_config *idle); bool prcmu_is_auto_pm_enabled(void); int prcmu_config_clkout(u8 clkout, u8 source, u8 div); -int prcmu_request_clock(u8 clock, bool enable); int prcmu_set_clock_divider(u8 clock, u8 divider); int prcmu_config_esram0_deep_sleep(u8 state); int prcmu_config_hotdog(u8 threshold); @@ -563,12 +559,17 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); void prcmu_ac_wake_req(void); void prcmu_ac_sleep_req(void); -void prcmu_system_reset(u16 reset_code); void prcmu_modem_reset(void); bool prcmu_is_ac_wake_requested(void); void prcmu_enable_spi2(void); void prcmu_disable_spi2(void); +void db8500_prcmu_system_reset(u16 reset_code); +int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); +void db8500_prcmu_enable_wakeups(u32 wakeups); +int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); +int db8500_prcmu_request_clock(u8 clock, bool enable); + #else /* !CONFIG_MFD_DB8500_PRCMU */ static inline int prcmu_set_rc_a2p(enum romcode_write code) @@ -586,14 +587,6 @@ static inline enum ap_pwrst prcmu_get_xp70_current_state(void) return AP_EXECUTE; } -static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, - bool keep_ap_pll) -{ - return 0; -} - -static inline void prcmu_enable_wakeups(u32 wakeups) {} - static inline void prcmu_disable_wakeups(void) {} static inline void prcmu_config_abb_event_readout(u32 abb_events) {} @@ -675,11 +668,6 @@ static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) return 0; } -static inline int prcmu_request_clock(u8 clock, bool enable) -{ - return 0; -} - static inline int prcmu_set_clock_divider(u8 clock, u8 divider) { return 0; @@ -724,8 +712,6 @@ static inline void prcmu_ac_wake_req(void) {} static inline void prcmu_ac_sleep_req(void) {} -static inline void prcmu_system_reset(u16 reset_code) {} - static inline void prcmu_modem_reset(void) {} static inline bool prcmu_is_ac_wake_requested(void) @@ -760,6 +746,26 @@ static inline int prcmu_disable_spi2(void) return 0; } +static inline void db8500_prcmu_system_reset(u16 reset_code) {} + +static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, + bool keep_ap_pll) +{ + return 0; +} + +static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {} + +static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state) +{ + return 0; +} + +static inline int db8500_prcmu_request_clock(u8 clock, bool enable) +{ + return 0; +} + #endif /* !CONFIG_MFD_DB8500_PRCMU */ #endif /* __MFD_DB8500_PRCMU_H */ |