diff options
| author | Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | 2009-03-25 13:10:01 +0200 |
|---|---|---|
| committer | Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | 2009-03-25 13:10:01 +0200 |
| commit | 28853ac8fe5221de74a14f1182d7b2b383dfd85c (patch) | |
| tree | dcfd9b20028e5a3a9504e26d2c9060f4746fc83a /arch/arm/boot/compressed | |
| parent | bba7d0b9ba0f04d25145de8170a17a3a07bbfdde (diff) | |
ARM: Add support for FA526 v2
Adds support for Faraday FA526 core. This core is used at least by:
Cortina Systems Gemini and Centroid family
Cavium Networks ECONA family
Grain Media GM8120
Pixelplus ImageARM
Prolific PL-1029
Faraday IP evaluation boards
v2:
- move TLB_BTB to separate patch
- update copyrights
Signed-off-by: Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
Diffstat (limited to 'arch/arm/boot/compressed')
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 77d614232d8..def02483286 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -459,6 +459,20 @@ __armv7_mmu_cache_on: mcr p15, 0, r0, c7, c5, 4 @ ISB mov pc, r12 +__fa526_cache_on: + mov r12, lr + bl __setup_mmu + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache + mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + mcr p15, 0, r0, c8, c7, 0 @ flush UTLB + mrc p15, 0, r0, c1, c0, 0 @ read control reg + orr r0, r0, #0x1000 @ I-cache enable + bl __common_mmu_cache_on + mov r0, #0 + mcr p15, 0, r0, c8, c7, 0 @ flush UTLB + mov pc, r12 + __arm6_mmu_cache_on: mov r12, lr bl __setup_mmu @@ -636,6 +650,12 @@ proc_types: b __armv4_mmu_cache_off b __armv5tej_mmu_cache_flush + .word 0x66015261 @ FA526 + .word 0xff01fff1 + b __fa526_cache_on + b __armv4_mmu_cache_off + b __fa526_cache_flush + @ These match on the architecture ID .word 0x00020000 @ ARMv4T @@ -775,6 +795,12 @@ __armv4_mpu_cache_flush: mcr p15, 0, ip, c7, c10, 4 @ drain WB mov pc, lr +__fa526_cache_flush: + mov r1, #0 + mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache + mcr p15, 0, r1, c7, c5, 0 @ flush I cache + mcr p15, 0, r1, c7, c10, 4 @ drain WB + mov pc, lr __armv6_mmu_cache_flush: mov r1, #0 |