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authorMadhu <madhu.cr@ti.com>2009-11-22 10:11:08 -0800
committerTony Lindgren <tony@atomide.com>2009-11-22 10:24:32 -0800
commit555d503ff30b3b1292d743bb77b19212b6befb59 (patch)
tree1e540873e6351a0a1e92c79eb326973eba9ee73e /arch/arm/plat-omap/include/plat/control.h
parent41fd03d66e6ae4430a0fdf7c62692a7b20b6ee6b (diff)
omap3630: Set omap3630 MMC1 I/O speed to 52Mhz
The speed ctrl bit for MMC I/O is part of CONTROL_PROG_IO1 register in omap3630.This patch sets it up accordingly. Signed-off-by: Madhusudhan Chikkature <madhu.cr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/plat-omap/include/plat/control.h')
-rw-r--r--arch/arm/plat-omap/include/plat/control.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 79985e497c4..2ae88437863 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -241,6 +241,9 @@
#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
#define OMAP2_PBIASLITEVMODE0 (1 << 0)
+/* CONTROL_PROG_IO1 bits */
+#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
+
/* CONTROL_IVA2_BOOTMOD bits */
#define OMAP3_IVA2_BOOTMOD_SHIFT 0
#define OMAP3_IVA2_BOOTMOD_MASK (0xf << 0)