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authorCatalin Marinas <catalin.marinas@arm.com>2008-10-22 13:04:30 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-22 19:40:21 +0100
commitf80a3bb252cbb0959259328b9ab02b019123ed05 (patch)
treebfc9cf861aa4ff025dbdf524c1b70700354ff7c1 /arch/arm
parent085eefb5948bb43020792f31406da2ee2ef4e924 (diff)
[ARM] 5318/1: Swap the PRRR and NMRR values in proc-v7.S
A typo caused these values to be swapped leading to incorrect memory type attributes. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mm/proc-v7.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 34e42404192..07f82db7094 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -180,8 +180,8 @@ __v7_setup:
mov r10, #0x1f @ domains 0, 1 = manager
mcr p15, 0, r10, c3, c0, 0 @ load domain access register
#endif
- ldr r5, =0x40e040e0
- ldr r6, =0xff0aa1a8
+ ldr r5, =0xff0aa1a8
+ ldr r6, =0x40e040e0
mcr p15, 0, r5, c10, c2, 0 @ write PRRR
mcr p15, 0, r6, c10, c2, 1 @ write NMRR
adr r5, v7_crval