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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-16 11:49:58 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-16 11:49:58 -0700 |
| commit | 8d6cea5111f2daea8acf79d7b4b384a14175ecc1 (patch) | |
| tree | ef56294da7eefbe46654b030fa8be06830a9c4f0 /arch/blackfin/mach-common/cache-c.c | |
| parent | 6a454f71d795368c00d9c329b60cc4d58929e7bc (diff) | |
| parent | 61cdd7a28f8b515140cb5d8aea518678f0fae024 (diff) | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (27 commits)
Blackfin: hook up new rt_tgsigqueueinfo syscall
Blackfin: improve CLKIN_HZ config default
Blackfin: initial support for ftrace grapher
Blackfin: initial support for ftrace
Blackfin: enable support for LOCKDEP
Blackfin: add preliminary support for STACKTRACE
Blackfin: move custom sections into sections.h
Blackfin: punt unused/wrong mutex-dec.h
Blackfin: add support for irqflags
Blackfin: add support for bzip2/lzma compressed kernel images
Blackfin: convert Kconfig style to def_bool
Blackfin: bf548-ezkit: update smsc911x resources
Blackfin: update aedos-ipipe code to upstream 1.10-00
Blackfin: bf537-stamp: update ADP5520 resources
Blackfin: bf518f-ezbrd: fix SPI CS for SPI flash
Blackfin: define SPI IRQ in board resources
Blackfin: do not configure the UART early if on wrong processor
Blackfin: fix deadlock in SMP IPI handler
Blackfin: fix flag storage for irq funcs
Blackfin: push down exception oops checking
...
Diffstat (limited to 'arch/blackfin/mach-common/cache-c.c')
| -rw-r--r-- | arch/blackfin/mach-common/cache-c.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/blackfin/mach-common/cache-c.c b/arch/blackfin/mach-common/cache-c.c index e6ab1f81512..b59ce3cb380 100644 --- a/arch/blackfin/mach-common/cache-c.c +++ b/arch/blackfin/mach-common/cache-c.c @@ -16,9 +16,21 @@ void blackfin_invalidate_entire_dcache(void) { u32 dmem = bfin_read_DMEM_CONTROL(); - SSYNC(); bfin_write_DMEM_CONTROL(dmem & ~0xc); SSYNC(); bfin_write_DMEM_CONTROL(dmem); SSYNC(); } + +/* Invalidate the Entire Instruction cache by + * clearing IMC bit + */ +void blackfin_invalidate_entire_icache(void) +{ + u32 imem = bfin_read_IMEM_CONTROL(); + bfin_write_IMEM_CONTROL(imem & ~0x4); + SSYNC(); + bfin_write_IMEM_CONTROL(imem); + SSYNC(); +} + |