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authorMagnus Damm <damm@opensource.se>2010-02-19 09:12:00 +0000
committerPaul Mundt <lethal@linux-sh.org>2010-02-22 19:11:19 +0900
commitde7ca2144c36291a491bd39afad172f56432a4bb (patch)
tree1a86bde64f584151b4213e8b70bcbe3ac4bfbfc4 /arch/sh/kernel/cpu
parent8c563a30cdfff2833c4c2078d25b5d1469706a6d (diff)
sh: clock-cpg div4 set_rate() shift fix
Make sure the div4 bitfield is shifted according to the enable_bit value in sh_clk_div4_set_rate(). Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu')
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index 2827abb5d2a..72a5e621a9b 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -192,8 +192,8 @@ static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id
return idx;
value = __raw_readl(clk->enable_reg);
- value &= ~0xf;
- value |= idx;
+ value &= ~(0xf << clk->enable_bit);
+ value |= (idx << clk->enable_bit);
__raw_writel(value, clk->enable_reg);
return 0;