diff options
| author | Mattias Nilsson <mattias.i.nilsson@stericsson.com> | 2011-09-12 11:49:13 +0200 |
|---|---|---|
| committer | Jonas ABERG <jonas.aberg@stericsson.com> | 2011-09-29 09:07:24 +0200 |
| commit | 9e7cead4b8c0c3e182c90653565c292a73b7dea1 (patch) | |
| tree | 4fe9616ba307d2a60040673190d7f15d14139500 /drivers/mfd/dbx500-prcmu-regs.h | |
| parent | 69aea9a09b41410c04564a23d59da09267192da3 (diff) | |
u8500: change clk_get_rate for prcmu clocks
This patch changes the implementation of clk_get_rate for
PRCMU clocks, so that it returns a rate according to the
hardware settings instead of a hardcoded value.
ST Ericsson ID: 343004, 359227
ST Ericsson FOSS-OUT ID: trivial
ST Ericsson Linux next: -
Change-Id: I9a4ff57884017dd22774553c5bcabbb0756a604f
Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/32138
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
Tested-by: Jonas ABERG <jonas.aberg@stericsson.com>
Diffstat (limited to 'drivers/mfd/dbx500-prcmu-regs.h')
| -rw-r--r-- | drivers/mfd/dbx500-prcmu-regs.h | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h index 457fa4dc212..d8a916becf5 100644 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ b/drivers/mfd/dbx500-prcmu-regs.h @@ -133,6 +133,18 @@ #define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) /* PRCMU clock/PLL/reset registers */ +#define PRCM_PLLSOC0_FREQ 0x080 +#define PRCM_PLLSOC1_FREQ 0x084 +#define PRCM_PLLDDR_FREQ 0x08C +#define PRCM_PLL_FREQ_D_SHIFT 0 +#define PRCM_PLL_FREQ_D_MASK BITS(0, 7) +#define PRCM_PLL_FREQ_N_SHIFT 8 +#define PRCM_PLL_FREQ_N_MASK BITS(8, 13) +#define PRCM_PLL_FREQ_R_SHIFT 16 +#define PRCM_PLL_FREQ_R_MASK BITS(16, 18) +#define PRCM_PLL_FREQ_SELDIV2 BIT(24) +#define PRCM_PLL_FREQ_DIV2EN BIT(25) + #define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) #define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) #define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508) @@ -184,9 +196,15 @@ #define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24) #define PRCM_CLKOCR_CLK1TYPE BIT(28) -#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) -#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) -#define PRCM_CLK_MGT_CLKEN BIT(8) +#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4) +#define PRCM_CLK_MGT_CLKPLLSW_SOC0 BIT(5) +#define PRCM_CLK_MGT_CLKPLLSW_SOC1 BIT(6) +#define PRCM_CLK_MGT_CLKPLLSW_DDR BIT(7) +#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7) +#define PRCM_CLK_MGT_CLKEN BIT(8) +#define PRCM_CLK_MGT_CLK38 BIT(9) +#define PRCM_CLK_MGT_CLK38DIV BIT(11) +#define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN BIT(12) /* GPIOCR register */ #define PRCM_GPIOCR_SPI2_SELECT BIT(23) |