diff options
| -rw-r--r-- | arch/arm/mach-ux500/devices-db8500.c | 65 |
1 files changed, 64 insertions, 1 deletions
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 4148a28be47..316c90a87a5 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -99,11 +99,17 @@ static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = { [DB8500_DMA_DEV1_SD_MMC0_TX] = -1, [DB8500_DMA_DEV2_SD_MMC1_TX] = -1, [DB8500_DMA_DEV3_SD_MMC2_TX] = -1, - [DB8500_DMA_DEV8_SSP0_TX] = -1, + [DB8500_DMA_DEV4_I2C1_TX] = -1, + [DB8500_DMA_DEV5_I2C3_TX] = -1, + [DB8500_DMA_DEV6_I2C2_TX] = -1, + [DB8500_DMA_DEV7_I2C4_TX] = -1, + [DB8500_DMA_DEV8_SSP0_TX] = U8500_SSP0_BASE + SSP_TX_RX_REG_OFFSET, [DB8500_DMA_DEV9_SSP1_TX] = -1, [DB8500_DMA_DEV11_UART2_TX] = -1, [DB8500_DMA_DEV12_UART1_TX] = -1, [DB8500_DMA_DEV13_UART0_TX] = -1, + [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, + [DB8500_DMA_DEV15_I2C0_TX] = -1, [DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0] = U8500_HSIT_BASE + 0x0 + STE_HSI_TX_BUFFERX, [DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1] @@ -112,15 +118,44 @@ static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = { = U8500_HSIT_BASE + 0x8 + STE_HSI_TX_BUFFERX, [DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3] = U8500_HSIT_BASE + 0xC + STE_HSI_TX_BUFFERX, + [DB8500_DMA_DEV24_DST_SXA0_RX_TX] = -1, + [DB8500_DMA_DEV25_DST_SXA1_RX_TX] = -1, + [DB8500_DMA_DEV26_DST_SXA2_RX_TX] = -1, + [DB8500_DMA_DEV27_DST_SXA3_RX_TX] = -1, [DB8500_DMA_DEV28_SD_MM2_TX] = -1, [DB8500_DMA_DEV29_SD_MM0_TX] = -1, + [DB8500_DMA_DEV30_MSP1_TX] + = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET, + [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] + = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, [DB8500_DMA_DEV32_SD_MM1_TX] = -1, [DB8500_DMA_DEV33_SPI2_TX] = -1, + [DB8500_DMA_DEV34_I2C3_TX2] = -1, [DB8500_DMA_DEV35_SPI1_TX] = -1, [DB8500_DMA_DEV40_SPI3_TX] = -1, [DB8500_DMA_DEV41_SD_MM3_TX] = -1, [DB8500_DMA_DEV42_SD_MM4_TX] = -1, [DB8500_DMA_DEV43_SD_MM5_TX] = -1, + [DB8500_DMA_DEV44_DST_SXA4_RX_TX] = -1, + [DB8500_DMA_DEV45_DST_SXA5_RX_TX] = -1, + [DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX] = -1, + [DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX] = -1, + [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET, + [DB8500_DMA_DEV49_CAC1_TX_HAC1_TX] = -1, + [DB8500_DMA_DEV50_HAC1_TX] = -1, + [DB8500_DMA_MEMCPY_TX_0] = -1, + [DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4] = -1, + [DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5] = -1, + [DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6] = -1, + [DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7] = -1, + [DB8500_DMA_MEMCPY_TX_1] = -1, + [DB8500_DMA_MEMCPY_TX_2] = -1, + [DB8500_DMA_MEMCPY_TX_3] = -1, + [DB8500_DMA_MEMCPY_TX_4] = -1, + [DB8500_DMA_MEMCPY_TX_5] = -1, + [DB8500_DMA_DEV61_CAC0_TX] = -1, + [DB8500_DMA_DEV62_CAC0_TX_HAC0_TX] = -1, + [DB8500_DMA_DEV63_HAC0_TX] = -1, }; /* Mapping between source event lines and physical device address */ @@ -139,11 +174,17 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = { [DB8500_DMA_DEV1_SD_MMC0_RX] = -1, [DB8500_DMA_DEV2_SD_MMC1_RX] = -1, [DB8500_DMA_DEV3_SD_MMC2_RX] = -1, + [DB8500_DMA_DEV4_I2C1_RX] = -1, + [DB8500_DMA_DEV5_I2C3_RX] = -1, + [DB8500_DMA_DEV6_I2C2_RX] = -1, + [DB8500_DMA_DEV7_I2C4_RX] = -1, [DB8500_DMA_DEV8_SSP0_RX] = -1, [DB8500_DMA_DEV9_SSP1_RX] = -1, [DB8500_DMA_DEV11_UART2_RX] = -1, [DB8500_DMA_DEV12_UART1_RX] = -1, [DB8500_DMA_DEV13_UART0_RX] = -1, + [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, + [DB8500_DMA_DEV15_I2C0_RX] = -1, [DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0] = U8500_HSIR_BASE + 0x0 + STE_HSI_RX_BUFFERX, [DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1] @@ -152,15 +193,37 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = { = U8500_HSIR_BASE + 0x8 + STE_HSI_RX_BUFFERX, [DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3] = U8500_HSIR_BASE + 0xC + STE_HSI_RX_BUFFERX, + [DB8500_DMA_DEV24_SRC_SXA0_RX_TX] = -1, + [DB8500_DMA_DEV25_SRC_SXA1_RX_TX] = -1, + [DB8500_DMA_DEV26_SRC_SXA2_RX_TX] = -1, + [DB8500_DMA_DEV27_SRC_SXA3_RX_TX] = -1, [DB8500_DMA_DEV28_SD_MM2_RX] = -1, [DB8500_DMA_DEV29_SD_MM0_RX] = -1, + [DB8500_DMA_DEV30_MSP1_RX] + = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET, + [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] + = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, [DB8500_DMA_DEV32_SD_MM1_RX] = -1, [DB8500_DMA_DEV33_SPI2_RX] = -1, + [DB8500_DMA_DEV34_I2C3_RX2] = -1, [DB8500_DMA_DEV35_SPI1_RX] = -1, [DB8500_DMA_DEV40_SPI3_RX] = -1, [DB8500_DMA_DEV41_SD_MM3_RX] = -1, [DB8500_DMA_DEV42_SD_MM4_RX] = -1, [DB8500_DMA_DEV43_SD_MM5_RX] = -1, + [DB8500_DMA_DEV44_SRC_SXA4_RX_TX] = -1, + [DB8500_DMA_DEV45_SRC_SXA5_RX_TX] = -1, + [DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX] = -1, + [DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX] = -1, + [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET, + /* 49, 50 and 51 are not used */ + [DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4] = -1, + [DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5] = -1, + [DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6] = -1, + [DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7] = -1, + /* 56, 57, 58, 59 and 60 are not used */ + [DB8500_DMA_DEV61_CAC0_RX] = -1, + /* 62 and 63 are not used */ }; /* Reserved event lines for memcpy only */ |