diff options
| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-12-17 16:53:07 +0100 |
| commit | cb5473205206c7f14cbb1e747f28ec75b48826e2 (patch) | |
| tree | 8f4808d60917100b18a10b05230f7638a0a9bbcc /board/amcc/acadia/memory.c | |
| parent | baf449fc5ff96f071bb0e3789fd3265f6d4fd9a0 (diff) | |
| parent | 92c78a3bbcb2ce508b4bf1c4a1e0940406a024bb (diff) | |
Merge branch 'fixes' into cleanups
Conflicts:
board/atmel/atngw100/atngw100.c
board/atmel/atstk1000/atstk1000.c
cpu/at32ap/at32ap700x/gpio.c
include/asm-avr32/arch-at32ap700x/clk.h
include/configs/atngw100.h
include/configs/atstk1002.h
include/configs/atstk1003.h
include/configs/atstk1004.h
include/configs/atstk1006.h
include/configs/favr-32-ezkit.h
include/configs/hammerhead.h
include/configs/mimc200.h
Diffstat (limited to 'board/amcc/acadia/memory.c')
| -rw-r--r-- | board/amcc/acadia/memory.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 48a672574..3e5c80ea4 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -39,7 +39,7 @@ static void cram_bcr_write(u32 wr_val) wr_val <<= 2; /* set CRAM_CRE to 1 */ - gpio_write_bit(CFG_GPIO_CRAM_CRE, 1); + gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1); /* Write BCR to CRAM on CS1 */ out32(wr_val + 0x00200000, 0); @@ -53,7 +53,7 @@ static void cram_bcr_write(u32 wr_val) eieio(); /* set CRAM_CRE back to 0 (normal operation) */ - gpio_write_bit(CFG_GPIO_CRAM_CRE, 0); + gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0); return; } @@ -75,10 +75,10 @@ phys_size_t initdram(int board_type) u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ - gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); - gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0); + gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); /* 2. EBC in Async mode */ mtebc(pb1ap, 0x078F1EC0); @@ -94,8 +94,8 @@ phys_size_t initdram(int board_type) mtebc(pb2ap, 0x9C0201C0); /* Set GPIO pins back to alternate function */ - gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); - gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); + gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); /* Config EBC to use RDY */ mfsdr(sdrultra0, val); @@ -106,5 +106,5 @@ phys_size_t initdram(int board_type) ; #endif - return (CFG_MBYTES_RAM << 20); + return (CONFIG_SYS_MBYTES_RAM << 20); } |