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authorStefan Roese <sr@denx.de>2007-10-31 20:57:11 +0100
committerStefan Roese <sr@denx.de>2007-10-31 21:21:47 +0100
commitea2e142843533ca593fcb5cb3e1daf1b7f5e5949 (patch)
treefb4c89b7d5b706e676c9ab8d4afcaf8d1373c21a /board/amcc/sequoia
parent3db93b8bedd32e914b38976141b3fdf4ea3ff738 (diff)
ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAM
This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/sequoia')
-rw-r--r--board/amcc/sequoia/init.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 5fe3af9a0..c7da5216d 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -98,7 +98,11 @@ tlbtab:
#endif
/* TLB-entry for DDR SDRAM (Up to 2GB) */
+#ifdef CONFIG_4xx_DCACHE
+ tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+#else
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#endif
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */