8548cds PCIE support.

Make the early L1 cache stack region guarded to prevent speculative
fetches outside the locked range.

Use _PHYS defines, not _MEM for cpu-side PCI memory mapped regions.
init.S whitespace cleanup.

Allow TEXT_BASE value to be specified on command line.  This allows it
to be set to 0xfffc0000 which cuts the uboot binary in half.

Clear and enable lbc and ecm errors.

Update last_busno in device-tree for pci and pcie.

Remove load of obsolete cpu/mpc85xx/pci.0

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

4 files changed, 291 insertions, 115 deletions

diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk
index 242a67620..b23bc8737 100644
--- a/board/cds/mpc8548cds/config.mk
+++ b/board/cds/mpc8548cds/config.mk
@@ -1,5 +1,5 @@
 #
-# Copyright 2004 Freescale Semiconductor.
+# Copyright 2004, 2007 Freescale Semiconductor.
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -23,7 +23,9 @@
 #
 # mpc8548cds board
 #
+ifndef TEXT_BASE
 TEXT_BASE = 0xfff80000
+endif
 
 PLATFORM_CPPFLAGS += -DCONFIG_E500=1
 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S
index d468f5b61..72940b035 100644
--- a/board/cds/mpc8548cds/init.S
+++ b/board/cds/mpc8548cds/init.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
  * Copyright 2002,2003, Motorola Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,12 @@
 #include <config.h>
 #include <mpc85xx.h>
 
+#define LAWAR_TRGT_PCI1		0x00000000
+#define LAWAR_TRGT_PCI2		0x00100000
+#define LAWAR_TRGT_PCIE		0x00200000
+#define LAWAR_TRGT_RIO		0x00c00000
+#define LAWAR_TRGT_LBC		0x00400000
+#define LAWAR_TRGT_DDR		0x00f00000
 
 /*
  * TLB0 and TLB1 Entries
@@ -47,8 +53,8 @@
  */
 
 #define	entry_start \
-	mflr	r1 	;	\
-	bl	0f 	;
+	mflr	r1	;	\
+	bl	0f	;
 
 #define	entry_end \
 0:	mflr	r0	;	\
@@ -84,8 +90,8 @@ tlb1_entry:
 #endif
 
 	/*
-	 * TLB0		16K	Cacheable, non-guarded
-	 * 0xd001_0000	16K	Temporary Global data for initialization
+	 * TLB0		16K	Cacheable, guarded
+	 * Temporary Global data for initialization
 	 *
 	 * Use four 4K TLB0 entries.  These entries must be cacheable
 	 * as they provide the bootstrap memory before the memory
@@ -97,28 +103,28 @@ tlb1_entry:
 	.long TLB1_MAS0(0, 0, 0)
 	.long TLB1_MAS1(1, 0, 0, 0, 0)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
-			0,0,0,0,0,0,0,0)
+			0,0,0,0,0,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
 			0,0,0,0,0,1,0,1,0,1)
 
 	.long TLB1_MAS0(0, 0, 0)
 	.long TLB1_MAS1(1, 0, 0, 0, 0)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
-			0,0,0,0,0,0,0,0)
+			0,0,0,0,0,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
 			0,0,0,0,0,1,0,1,0,1)
 
 	.long TLB1_MAS0(0, 0, 0)
 	.long TLB1_MAS1(1, 0, 0, 0, 0)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
-			0,0,0,0,0,0,0,0)
+			0,0,0,0,0,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
 			0,0,0,0,0,1,0,1,0,1)
 
 	.long TLB1_MAS0(0, 0, 0)
 	.long TLB1_MAS1(1, 0, 0, 0, 0)
 	.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
-			0,0,0,0,0,0,0,0)
+			0,0,0,0,0,0,1,0)
 	.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
 			0,0,0,0,0,1,0,1,0,1)
 
@@ -130,51 +136,44 @@ tlb1_entry:
 	 */
 	.long TLB1_MAS0(1, 0, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLB 1:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM
+	 * TLB 1:	1G	Non-cacheable, guarded
+	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
 	 */
 	.long TLB1_MAS0(1, 1, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
 
+#ifdef CFG_RIO_MEM_PHYS
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI2 MEM
 	 */
 	.long TLB1_MAS0(1, 2, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE),
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
 			0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE),
-			0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS),	0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLB 3:	1GB	Non-cacheable, guarded
-	 * 0xa0000000	256M	PEX MEM First half
-	 * 0xb0000000	256M	PEX MEM Second half
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 * 0xd0000000	256M	Rapid IO MEM Second half
+	 * TLB 3:	256M	Non-cacheable, guarded
 	 */
 	.long TLB1_MAS0(1, 3, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
-	/*
-	 * TLB 4:	Reserved for future usage
-	 */
-
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
+			0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
+			0,0,0,0,0,1,0,1,0,1)
+#endif
 	/*
 	 * TLB 5:	64M	Non-cacheable, guarded
 	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe200_0000	8M	PCI1 IO
-	 * 0xe280_0000	8M	PCI2 IO
-	 * 0xe300_0000	16M	PEX IO
+	 * 0xe200_0000	1M	PCI1 IO
+	 * 0xe210_0000	1M	PCI2 IO
+	 * 0xe300_0000	1M	PCIe IO
 	 */
 	.long TLB1_MAS0(1, 5, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
@@ -187,17 +186,18 @@ tlb1_entry:
 	 */
 	.long TLB1_MAS0(1, 6, 0)
 	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
-	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
 
 	/*
-	 * TLB 7:	1M	Non-cacheable, guarded
-	 * 0xf8000000	1M	CADMUS registers
+	 * TLB 7:	64M	Non-cacheable, guarded
+	 * 0xf8000000	64M	CADMUS registers, relocated L2SRAM
 	 */
 	.long TLB1_MAS0(1, 7, 0)
-	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
-	.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
-	.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+	.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+	.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
+	.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
 2:
 	entry_end
 
@@ -205,14 +205,13 @@ tlb1_entry:
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x8fff_ffff     PCI1 MEM                256M
- * 0x9000_0000     0x9fff_ffff     PCI2 MEM                256M
- * 0xa000_0000     0xbfff_ffff     PEX MEM                 512M
+ * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
  * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe27f_ffff     PCI1 IO                 8M
- * 0xe280_0000     0xe2ff_ffff     PCI2 IO                 8M
- * 0xe300_0000     0xe3ff_ffff     PEX IO                  16M
+ * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
+ * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
+ * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
  * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
@@ -222,47 +221,50 @@ tlb1_entry:
  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
  *    If flash is 8M at default position (last 8M), no LAW needed.
  *
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ * LAW 0 is reserved for boot mapping
  */
 
-#define LAWBAR0 0
-#define LAWAR0  ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+	.section .bootpg, "ax"
+	.globl	law_entry
+law_entry:
+	entry_start
 
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+	.long (4f-3f)/8
+3:
+	.long  0
+	.long  (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
 
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+#ifdef CFG_PCI1_MEM_PHYS
+	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
 
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 	(LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#ifdef CFG_PCI2_MEM_PHYS
+	.long	(CFG_PCI2_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
-#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR6 	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+	.long	(CFG_PCI2_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
 
-#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR7 	(LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#ifdef CFG_PCIE1_MEM_PHYS
+	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
 
-#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR8  (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
 
-	.section .bootpg, "ax"
-	.globl	law_entry
+	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
 
-law_entry:
-	entry_start
-	.long (4f-3f)/8
-3:
-	.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
-	.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7
-	.long LAWBAR8,LAWAR8
+#ifdef CFG_RIO_MEM_PHYS
+	.long	(CFG_RIO_MEM_PHYS>>12) & 0xfffff
+	.long	LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+#endif
 4:
 	entry_end
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
index b7236417e..242a68c39 100644
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
  *
  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  *
@@ -26,6 +26,7 @@
 #include <pci.h>
 #include <asm/processor.h>
 #include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
 #include <spd.h>
 #include <miiphy.h>
 
@@ -33,10 +34,15 @@
 #include "../common/eeprom.h"
 #include "../common/via.h"
 
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
+DECLARE_GLOBAL_DATA_PTR;
+
 extern long int spd_sdram(void);
 
 void local_bus_init(void);
@@ -56,13 +62,6 @@ int checkboard (void)
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
 
-	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
-	uint pci1_32 = gur->pordevsr & 0x10000;	/* PORDEVSR[15] */
-	uint pci1_clk_sel = gur->porpllsr & 0x8000;	/* PORPLLSR[16] */
-	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
-
-	uint pci1_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
-
 	uint cpu_board_rev = get_cpu_board_revision ();
 
 	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
@@ -71,20 +70,6 @@ int checkboard (void)
 	printf ("CPU Board Revision %d.%d (0x%04x)\n",
 		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
 		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
-	printf ("    PCI1: %d bit, %s MHz, %s\n",
-		(pci1_32) ? 32 : 64,
-		(pci1_speed == 33000000) ? "33" :
-		(pci1_speed == 66000000) ? "66" : "unknown",
-		pci1_clk_sel ? "sync" : "async");
-
-	if (pci_dual) {
-		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
-			pci2_clk_sel ? "sync" : "async");
-	} else {
-		printf ("    PCI2: disabled\n");
-	}
-
 	/*
 	 * Initialize local bus.
 	 */
@@ -102,6 +87,8 @@ int checkboard (void)
 	 */
 	gur->tsec34ioovcr = 0xe7e0;	/*  1110 0111 1110 0xxx */
 
+	ecm->eedr = 0xffffffff;		/* clear ecm errors */
+	ecm->eeer = 0xffffffff;		/* enable ecm errors */
 	return 0;
 }
 
@@ -176,6 +163,9 @@ local_bus_init(void)
 	lbc->lcrr |= 0x00030000;
 
 	asm("sync;isync;msync");
+
+	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
+	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
 }
 
 /*
@@ -301,7 +291,7 @@ testdram(void)
 }
 #endif
 
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
 /* For some reason the Tundra PCI bridge shows up on itself as a
  * different device.  Work around that by refusing to configure it.
  */
@@ -320,21 +310,175 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = {
 	{},
 };
 
-static struct pci_controller hose[] = {
-	{ config_table: pci_mpc85xxcds_config_table,},
-#ifdef CONFIG_MPC85XX_PCI2
-	{},
-#endif
-};
-
+static struct pci_controller pci1_hose = {
+	config_table: pci_mpc85xxcds_config_table};
 #endif	/* CONFIG_PCI */
 
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif	/* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif	/* CONFIG_PCIE1 */
+
+int first_free_busno=0;
+
 void
 pci_init_board(void)
 {
-#ifdef CONFIG_PCI
-	pci_mpc85xx_init(&hose);
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_gur_t *gur = &immap->im_gur;
+	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+
+#ifdef CONFIG_PCI1
+{
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pci1_hose;
+	struct pci_config_table *table;
+
+	uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
+	uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;	/* PORDEVSR[14] */
+	uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;	/* PORPLLSR[16] */
+
+	uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+	uint pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
+
+	if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+		printf ("    PCI: %d bit, %s MHz, %s, %s, %s\n",
+			(pci_32) ? 32 : 64,
+			(pci_speed == 33333000) ? "33" :
+			(pci_speed == 66666000) ? "66" : "unknown",
+			pci_clk_sel ? "sync" : "async",
+			pci_agent ? "agent" : "host",
+			pci_arb ? "arbiter" : "external-arbiter"
+			);
+
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 0,
+			       CFG_PCI1_MEM_BASE,
+			       CFG_PCI1_MEM_PHYS,
+			       CFG_PCI1_MEM_SIZE,
+			       PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 1,
+			       CFG_PCI1_IO_BASE,
+			       CFG_PCI1_IO_PHYS,
+			       CFG_PCI1_IO_SIZE,
+			       PCI_REGION_IO);
+		hose->region_count = 2;
+
+		/* relocate config table pointers */
+		hose->config_table = \
+			(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
+		for (table = hose->config_table; table && table->vendor; table++)
+			table->config_device += gd->reloc_off;
+
+		hose->first_busno=first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		first_free_busno=hose->last_busno+1;
+		printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+#ifdef CONFIG_PCIX_CHECK
+		if (!(gur->pordevsr & PORDEVSR_PCI)) {
+			/* PCI-X init */
+			if (CONFIG_SYS_CLK_FREQ < 66000000)
+				printf("PCI-X will only work at 66 MHz\n");
+
+			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+		}
 #endif
+	} else {
+		printf ("    PCI: disabled\n");
+	}
+}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+	uint pci2_clk_sel = gur->porpllsr & 0x4000;	/* PORPLLSR[17] */
+	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
+	if (pci_dual) {
+		printf ("    PCI2: 32 bit, 66 MHz, %s\n",
+			pci2_clk_sel ? "sync" : "async");
+	} else {
+		printf ("    PCI2: disabled\n");
+	}
+}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+{
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	extern void fsl_pci_init(struct pci_controller *hose);
+	struct pci_controller *hose = &pcie1_hose;
+	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+	int pcie_configured  = io_sel >= 1;
+
+	if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+		printf ("\n    PCIE connected to slot as %s (base address %x)",
+			pcie_ep ? "End Point" : "Root Complex",
+			(uint)pci);
+
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
+		}
+		printf ("\n");
+
+		/* inbound */
+		pci_set_region(hose->regions + 0,
+			       CFG_PCI_MEMORY_BUS,
+			       CFG_PCI_MEMORY_PHYS,
+			       CFG_PCI_MEMORY_SIZE,
+			       PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+		/* outbound memory */
+		pci_set_region(hose->regions + 1,
+			       CFG_PCIE1_MEM_BASE,
+			       CFG_PCIE1_MEM_PHYS,
+			       CFG_PCIE1_MEM_SIZE,
+			       PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(hose->regions + 2,
+			       CFG_PCIE1_IO_BASE,
+			       CFG_PCIE1_IO_PHYS,
+			       CFG_PCIE1_IO_SIZE,
+			       PCI_REGION_IO);
+
+		hose->region_count = 3;
+
+		hose->first_busno=first_free_busno;
+		pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+		fsl_pci_init(hose);
+		printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
+
+		first_free_busno=hose->last_busno+1;
+
+	} else {
+		printf ("    PCIE: disabled\n");
+	}
+ }
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
 }
 
 int last_stage_init(void)
@@ -367,3 +511,32 @@ int last_stage_init(void)
 
 	return 0;
 }
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	u32 *p;
+	int len;
+
+
+#ifdef CONFIG_PCI1
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+	if (p != NULL) {
+		p[0] = 0;
+		p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+		debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+	}
+#endif
+
+#ifdef CONFIG_PCIE1
+	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
+	if (p != NULL) {
+		p[0] = 0;
+		p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+		debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+	}
+#endif
+}
+#endif
diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds
index c1f3495d7..530ba5a72 100644
--- a/board/cds/mpc8548cds/u-boot.lds
+++ b/board/cds/mpc8548cds/u-boot.lds
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -71,7 +71,6 @@ SECTIONS
     cpu/mpc85xx/cpu.o (.text)
     drivers/tsec.o (.text)
     cpu/mpc85xx/speed.o (.text)
-    cpu/mpc85xx/pci.o (.text)
     common/dlmalloc.o (.text)
     lib_generic/crc32.o (.text)
     lib_ppc/extable.o (.text)