Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

1 files changed, 111 insertions, 111 deletions

diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h
index 5a2d15770..971338a46 100644
--- a/include/configs/P3G4.h
+++ b/include/configs/P3G4.h
@@ -40,7 +40,7 @@
  */
 
 #define CONFIG_P3G4		1	/* this is a P3G4  board	*/
-#define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
+#define CONFIG_SYS_GT_6426x        GT_64260 /* with a 64260 system controller */
 
 #define CONFIG_BAUDRATE		115200	/* console baudrate = 115200	*/
 
@@ -51,10 +51,10 @@
 #define CONFIG_MISC_INIT_R	1
 #define CONFIG_BOARD_EARLY_INIT_F 1
 
-#define CFG_BOARD_NAME		"P3G4"
+#define CONFIG_SYS_BOARD_NAME		"P3G4"
 
-#undef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
+#undef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * The following defines let you select what serial you want to use
@@ -115,7 +115,7 @@
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
-#define	CFG_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
+#define	CONFIG_SYS_LOADS_BAUD_CHANGE		/* allow baudrate changes	*/
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 #undef	CONFIG_ALTIVEC                  /* undef to disable             */
@@ -151,27 +151,27 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_LONGHELP			/* undef to save memory		*/
-#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
+#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define	CFG_MAXARGS	16		/* max number of command args	*/
-#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_MEMTEST_START	0x00400000	/* memtest works on	*/
-#define CFG_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
+#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
+#define CONFIG_SYS_MEMTEST_END		0x00C00000	/* 4 ... 12 MB in DRAM	*/
 
-#define	CFG_LOAD_ADDR		0x00300000	/* default load address	*/
+#define	CONFIG_SYS_LOAD_ADDR		0x00300000	/* default load address	*/
 
-#define	CFG_HZ			1000		/* decr freq: 1ms ticks	*/
-#define CFG_BUS_HZ		133000000	/* 133 MHz		*/
-#define CFG_BUS_CLK		CFG_BUS_HZ
+#define	CONFIG_SYS_HZ			1000		/* decr freq: 1ms ticks	*/
+#define CONFIG_SYS_BUS_HZ		133000000	/* 133 MHz		*/
+#define CONFIG_SYS_BUS_CLK		CONFIG_SYS_BUS_HZ
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
 
 
 /*
@@ -183,63 +183,63 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
-#define CFG_INIT_RAM_ADDR	0x40000000
-#define	CFG_INIT_RAM_END	0x1000
-#define	CFG_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0x40000000
+#define	CONFIG_SYS_INIT_RAM_END	0x1000
+#define	CONFIG_SYS_GBL_DATA_SIZE	128  /* size in bytes reserved for init data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_LOCK
 
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
-#define CFG_FLASH_BASE		0xff000000
-#define CFG_RESET_ADDRESS	0xfff00100
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
+#define CONFIG_SYS_FLASH_BASE		0xff000000
+#define CONFIG_SYS_RESET_ADDRESS	0xfff00100
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc */
 
 /* areas to map different things with the GT in physical space */
-#define CFG_DRAM_BANKS		1
-#define CFG_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
+#define CONFIG_SYS_DRAM_BANKS		1
+#define CONFIG_SYS_DFL_GT_REGS		0x14000000	/* boot time GT_REGS */
 
 /* What to put in the bats. */
-#define CFG_MISC_REGION_BASE	0xf0000000
+#define CONFIG_SYS_MISC_REGION_BASE	0xf0000000
 
 /* Peripheral Device section */
-#define CFG_GT_REGS		0xf8000000
-#define CFG_DEV_BASE		0xff000000
+#define CONFIG_SYS_GT_REGS		0xf8000000
+#define CONFIG_SYS_DEV_BASE		0xff000000
 
-#define CFG_DEV0_SPACE		CFG_DEV_BASE
-#define CFG_DEV1_SPACE		(CFG_DEV0_SPACE + CFG_DEV0_SIZE)
-#define CFG_DEV2_SPACE		(CFG_DEV1_SPACE + CFG_DEV1_SIZE)
-#define CFG_DEV3_SPACE		(CFG_DEV2_SPACE + CFG_DEV2_SIZE)
+#define CONFIG_SYS_DEV0_SPACE		CONFIG_SYS_DEV_BASE
+#define CONFIG_SYS_DEV1_SPACE		(CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE)
+#define CONFIG_SYS_DEV2_SPACE		(CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE)
+#define CONFIG_SYS_DEV3_SPACE		(CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE)
 
-#define CFG_DEV0_SIZE		 _8M /* Flash bank */
-#define CFG_DEV1_SIZE		 0   /* unused */
-#define CFG_DEV2_SIZE		 0   /* unused */
-#define CFG_DEV3_SIZE		 0   /* unused */
+#define CONFIG_SYS_DEV0_SIZE		 _8M /* Flash bank */
+#define CONFIG_SYS_DEV1_SIZE		 0   /* unused */
+#define CONFIG_SYS_DEV2_SIZE		 0   /* unused */
+#define CONFIG_SYS_DEV3_SIZE		 0   /* unused */
 
-#define CFG_16BIT_BOOT_PAR	0xc01b5e7c
-#define CFG_DEV0_PAR		CFG_16BIT_BOOT_PAR
+#define CONFIG_SYS_16BIT_BOOT_PAR	0xc01b5e7c
+#define CONFIG_SYS_DEV0_PAR		CONFIG_SYS_16BIT_BOOT_PAR
 
 #if 0 /* Wrong?? NTL */
-#define CFG_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
+#define CONFIG_SYS_MPP_CONTROL_0	0x53541717	/* InitAct EOT[4] DBurst TCEn[1] */
 						/* DMAAck[1:0] GNT0[1:0] */
 #else
-#define CFG_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
+#define CONFIG_SYS_MPP_CONTROL_0	0x53547777	/* InitAct EOT[4] DBurst TCEn[1] */
 						/* REQ0[1:0] GNT0[1:0] */
 #endif
-#define CFG_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
+#define CONFIG_SYS_MPP_CONTROL_1	0x44009911	/* TCEn[4] TCTcnt[4] GPP[13:12] */
 						/* DMAReq[4] DMAAck[4] WDNMI WDE */
 #if 0 /* Wrong?? NTL */
-#define CFG_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
+#define CONFIG_SYS_MPP_CONTROL_2	0x40091818	/* TCTcnt[0] GPP[22:21] BClkIn */
 						/* DMAAck[1:0] GNT1[1:0] */
 #else
-#define CFG_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
+#define CONFIG_SYS_MPP_CONTROL_2	0x40098888	/* TCTcnt[0] */
 						/* GPP[22] (RS232IntB or PCI1Int) */
 						/* GPP[21] (RS323IntA) */
 						/* BClkIn */
@@ -247,10 +247,10 @@
 #endif
 
 #if 0 /* Wrong?? NTL */
-# define CFG_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
+# define CONFIG_SYS_MPP_CONTROL_3	0x00090066	/* GPP[31:29] BClkOut0 */
 						/* GPP[27:26] Int[1:0] */
 #else
-# define CFG_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
+# define CONFIG_SYS_MPP_CONTROL_3	0x22090066      /* MREQ MGNT */
 						/* GPP[29]    (PCI1Int) */
 						/* BClkOut0 */
 						/* GPP[27]    (PCI0Int) */
@@ -258,17 +258,17 @@
 						/* CPUInt[25:24] */
 #endif
 
-#define CFG_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
+#define CONFIG_SYS_SERIAL_PORT_MUX	0x00001102	/* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */
 
 #if 0 /* Wrong?? - NTL */
-# define CFG_GPP_LEVEL_CONTROL	0x000002c6
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x000002c6
 #else
-# define CFG_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
+# define CONFIG_SYS_GPP_LEVEL_CONTROL	0x2c600000	/* 0010 1100 0110 0000 */
 						/* gpp[29] */
 						/* gpp[27:26] */
 						/* gpp[22:21] */
 
-# define CFG_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
+# define CONFIG_SYS_SDRAM_CONFIG	0xd8e18200	/* 0x448 */
 				/* idmas use buffer 1,1
 				   comm use buffer 0
 				   pci use buffer 1,1
@@ -286,13 +286,13 @@
 #endif
 
 #if 0
-#define CFG_DUART_IO		CFG_DEV2_SPACE
-#define CFG_DUART_CHAN		1		/* channel to use for console */
+#define CONFIG_SYS_DUART_IO		CONFIG_SYS_DEV2_SPACE
+#define CONFIG_SYS_DUART_CHAN		1		/* channel to use for console */
 #endif
-#undef CFG_INIT_CHAN1
-#undef CFG_INIT_CHAN2
+#undef CONFIG_SYS_INIT_CHAN1
+#undef CONFIG_SYS_INIT_CHAN2
 #if 0
-#define SRAM_BASE		CFG_DEV0_SPACE
+#define SRAM_BASE		CONFIG_SYS_DEV0_SPACE
 #define SRAM_SIZE		0x00100000		/* 1 MB of sram */
 #endif
 
@@ -311,24 +311,24 @@
 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 
 /* PCI MEMORY MAP section */
-#define CFG_PCI0_MEM_BASE	0x80000000
-#define CFG_PCI0_MEM_SIZE	_128M
-#define CFG_PCI0_0_MEM_SPACE	(CFG_PCI0_MEM_BASE)
+#define CONFIG_SYS_PCI0_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI0_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI0_0_MEM_SPACE	(CONFIG_SYS_PCI0_MEM_BASE)
 
-#define CFG_PCI1_MEM_BASE	0x88000000
-#define CFG_PCI1_MEM_SIZE	_128M
-#define CFG_PCI1_0_MEM_SPACE	(CFG_PCI1_MEM_BASE)
+#define CONFIG_SYS_PCI1_MEM_BASE	0x88000000
+#define CONFIG_SYS_PCI1_MEM_SIZE	_128M
+#define CONFIG_SYS_PCI1_0_MEM_SPACE	(CONFIG_SYS_PCI1_MEM_BASE)
 
 /* PCI I/O MAP section */
-#define CFG_PCI0_IO_BASE	0xfa000000
-#define CFG_PCI0_IO_SIZE	_16M
-#define CFG_PCI0_IO_SPACE	(CFG_PCI0_IO_BASE)
-#define CFG_PCI0_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI0_IO_BASE	0xfa000000
+#define CONFIG_SYS_PCI0_IO_SIZE	_16M
+#define CONFIG_SYS_PCI0_IO_SPACE	(CONFIG_SYS_PCI0_IO_BASE)
+#define CONFIG_SYS_PCI0_IO_SPACE_PCI	0x00000000
 
-#define CFG_PCI1_IO_BASE	0xfb000000
-#define CFG_PCI1_IO_SIZE	_16M
-#define CFG_PCI1_IO_SPACE	(CFG_PCI1_IO_BASE)
-#define CFG_PCI1_IO_SPACE_PCI	0x00000000
+#define CONFIG_SYS_PCI1_IO_BASE	0xfb000000
+#define CONFIG_SYS_PCI1_IO_SIZE	_16M
+#define CONFIG_SYS_PCI1_IO_SPACE	(CONFIG_SYS_PCI1_IO_BASE)
+#define CONFIG_SYS_PCI1_IO_SPACE_PCI	0x00000000
 
 /*----------------------------------------------------------------------
  * Initial BAT mappings
@@ -340,32 +340,32 @@
  */
 
 /* SDRAM */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
 
 /* init ram */
-#define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
+#define CONFIG_SYS_IBAT1L  (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U  (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 
 /* PCI0, PCI1 in one BAT */
-#define CFG_IBAT2L BATL_NO_ACCESS
-#define CFG_IBAT2U CFG_DBAT2U
-#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
+#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
+#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 
 /* GT regs, bootrom, all the devices, PCI I/O */
-#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
-#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
-#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U CFG_IBAT3U
+#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
+#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
+#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
 
 /* I2C speed and slave address (for compatability) defaults */
-#define CFG_I2C_SPEED	400000
-#define CFG_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_SPEED	400000
+#define CONFIG_SYS_I2C_SLAVE	0x7F
 
 /* I2C addresses for the two DIMM SPD chips */
 #ifndef CONFIG_EVB64260_750CX
@@ -381,33 +381,33 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
+#define	CONFIG_SYS_BOOTMAPSZ		(8<<20)	/* Initial Memory map for Linux */
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
-#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/
+#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip */
 
-#define CFG_EXTRA_FLASH_DEVICE	BOOT_DEVICE
-#define CFG_EXTRA_FLASH_WIDTH	2	/* 16 bit */
-#define CFG_BOOT_FLASH_WIDTH	2	/* 16 bit */
+#define CONFIG_SYS_EXTRA_FLASH_DEVICE	BOOT_DEVICE
+#define CONFIG_SYS_EXTRA_FLASH_WIDTH	2	/* 16 bit */
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	2	/* 16 bit */
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_CFI		1
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */
+#define CONFIG_SYS_FLASH_CFI		1
 
-#define	CFG_ENV_IS_IN_FLASH	1
-#define	CFG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
-#define CFG_ENV_SECT_SIZE	0x20000
-#define CFG_ENV_ADDR		0xFFFE0000
+#define	CONFIG_ENV_IS_IN_FLASH	1
+#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector */
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#define CONFIG_ENV_ADDR		0xFFFE0000
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For all MPC74xx CPUs		 */
 #if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
 /*-----------------------------------------------------------------------
@@ -415,7 +415,7 @@
  * look in include/74xx_7xx.h for the defines used here
  */
 
-#define CFG_L2
+#define CONFIG_SYS_L2
 
 #define L2_INIT		(L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 			 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
@@ -430,7 +430,7 @@
 #define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
 #define BOOTFLAG_WARM	0x02		/* Software reboot		    */
 
-#define CFG_BOARD_ASM_INIT      1
+#define CONFIG_SYS_BOARD_ASM_INIT      1
 
 
 #endif	/* __CONFIG_H */