diff options
| author | Wolfgang Denk <wd@denx.de> | 2009-11-24 23:13:06 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-11-24 23:13:06 +0100 |
| commit | 2f6f67da1b98b6d1dad2d80bc4e472c3bff3cd5a (patch) | |
| tree | d58d72b762cbbb17f3493206467e5c708b72ae82 /include | |
| parent | 4e574c4e2d3776d9db62dca4ca3c73be1574af43 (diff) | |
| parent | eb5eb2b0f744f0cba405160c5d01335c40f09acf (diff) | |
Merge branch 'next' of git://www.denx.de/git/u-boot-ppc4xx into next
Diffstat (limited to 'include')
| -rw-r--r-- | include/4xx_i2c.h | 38 | ||||
| -rw-r--r-- | include/ppc405.h | 19 | ||||
| -rw-r--r-- | include/ppc440.h | 19 |
3 files changed, 21 insertions, 55 deletions
diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h index 070657fbb..0c6c926f7 100644 --- a/include/4xx_i2c.h +++ b/include/4xx_i2c.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -52,22 +52,26 @@ #define I2C_BASE_ADDR (0xEF600500 + I2C_BUS_OFFS) #endif -#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR -#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF) -#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF) -#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR) -#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR) -#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL) -#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL) -#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS) -#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) -#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) -#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV) -#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) -#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) -#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) -#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL) +struct ppc4xx_i2c { + u8 mdbuf; + u8 res1; + u8 sdbuf; + u8 res2; + u8 lmadr; + u8 hmadr; + u8 cntl; + u8 mdcntl; + u8 sts; + u8 extsts; + u8 lsadr; + u8 hsadr; + u8 clkdiv; + u8 intrmsk; + u8 xfrcnt; + u8 xtcntlss; + u8 directcntl; + u8 intr; +}; /* MDCNTL Register Bit definition */ #define IIC_MDCNTL_HSCL 0x01 diff --git a/include/ppc405.h b/include/ppc405.h index 508c77b14..bc2d051fc 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -566,25 +566,6 @@ #define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ /*----------------------------------------------------------------------------- -| IIC Register Offsets -'----------------------------------------------------------------------------*/ -#define IICMDBUF 0x00 -#define IICSDBUF 0x02 -#define IICLMADR 0x04 -#define IICHMADR 0x05 -#define IICCNTL 0x06 -#define IICMDCNTL 0x07 -#define IICSTS 0x08 -#define IICEXTSTS 0x09 -#define IICLSADR 0x0A -#define IICHSADR 0x0B -#define IIC0_CLKDIV 0x0C -#define IICINTRMSK 0x0D -#define IICXFRCNT 0x0E -#define IICXTCNTLSS 0x0F -#define IICDIRECTCNTL 0x10 - -/*----------------------------------------------------------------------------- | UART Register Offsets '----------------------------------------------------------------------------*/ #define DATA_REG 0x00 diff --git a/include/ppc440.h b/include/ppc440.h index a050ffd1c..e60fa1390 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1714,25 +1714,6 @@ #endif /*----------------------------------------------------------------------------- -| IIC Register Offsets -'----------------------------------------------------------------------------*/ -#define IICMDBUF 0x00 -#define IICSDBUF 0x02 -#define IICLMADR 0x04 -#define IICHMADR 0x05 -#define IICCNTL 0x06 -#define IICMDCNTL 0x07 -#define IICSTS 0x08 -#define IICEXTSTS 0x09 -#define IICLSADR 0x0A -#define IICHSADR 0x0B -#define IIC0_CLKDIV 0x0C -#define IICINTRMSK 0x0D -#define IICXFRCNT 0x0E -#define IICXTCNTLSS 0x0F -#define IICDIRECTCNTL 0x10 - -/*----------------------------------------------------------------------------- | PCI Internal Registers et. al. (accessed via plb) +----------------------------------------------------------------------------*/ #define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) |