delta board: DA9030 initialization and i2c support. Some minor changes to

make the pxa i2c driver work with the monahans cpu.

3 files changed, 123 insertions, 7 deletions

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index a92a4504d..ebda7192e 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -475,11 +475,11 @@ typedef void		(*ExcpHndlr) (void) ;
 #define ICR_ACKNAK	0x4		/* send ACK(0) or NAK(1) */
 #define ICR_TB		0x8		/* transfer byte bit */
 #define ICR_MA		0x10		/* master abort */
-#define ICR_SCLE	0x20		/* master clock enable */
+#define ICR_SCLE	0x20		/* master clock enable, mona SCLEA */
 #define ICR_IUE		0x40		/* unit enable */
 #define ICR_GCD		0x80		/* general call disable */
 #define ICR_ITEIE	0x100		/* enable tx interrupts */
-#define ICR_IRFIE	0x200		/* enable rx interrupts */
+#define ICR_IRFIE	0x200		/* enable rx interrupts, mona: DRFIE */
 #define ICR_BEIE	0x400		/* enable bus error ints */
 #define ICR_SSDIE	0x800		/* slave STOP detected int enable */
 #define ICR_ALDIE	0x1000		/* enable arbitration interrupt */
@@ -923,7 +923,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define ICHP		__REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
 /* Missing: 32 Interrupt priority registers
  * These are the same as beneath for PXA27x: maybe can be merged if
- * GPIO Stuff is same too. 
+ * GPIO Stuff is same too.
  */
 #define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
 #define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
diff --git a/include/configs/delta.h b/include/configs/delta.h
index cb002f726..eaa4c432b 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -49,7 +49,6 @@
 /*
  * Hardware drivers
  */
-
 #undef TURN_ON_ETHERNET
 #ifdef TURN_ON_ETHERNET
 # define CONFIG_DRIVER_SMC91111 1
@@ -59,6 +58,12 @@
 # undef CONFIG_SMC_USE_IOFUNCS          /* just for use with the kernel */
 #endif
 
+#define CONFIG_HARD_I2C		1	/* required for DA9030 access */
+#define CFG_I2C_SPEED		400000	/* I2C speed */
+#define CFG_I2C_SLAVE		1	/* I2C controllers address */
+#define DA9030_I2C_ADDR		0x49	/* I2C address of DA9030 */
+/* #define CONFIG_HW_WATCHDOG	1	/\* Required for hitting the DA9030 WD *\/ */
+
 /*
  * select serial console configuration
  */
@@ -73,8 +78,13 @@
 #ifdef TURN_ON_ETHERNET
 # define CONFIG_COMMANDS        (CONFIG_CMD_DFL | CFG_CMD_PING)
 #else
-# define CONFIG_COMMANDS	((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \
-				& ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS))
+# define CONFIG_COMMANDS	((CONFIG_CMD_DFL \
+				  | CFG_CMD_ENV \
+				  | CFG_CMD_NAND \
+				  | CFG_CMD_I2C) \
+				 & ~(CFG_CMD_NET \
+				     | CFG_CMD_FLASH \
+				     | CFG_CMD_IMLS))
 #endif
 
 
@@ -121,7 +131,7 @@
 
 #define CFG_LOAD_ADDR	(CFG_DRAM_BASE + 0x8000) /* default load address */
 
-#define CFG_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CFG_HZ			3250000		/* incrementer freq: 3.25 MHz */
 #define CFG_CPUSPEED		0x161		/* set core clock to 400/200/100 MHz */
 
 						/* valid baudrates */
diff --git a/include/da9030.h b/include/da9030.h
new file mode 100644
index 000000000..41108b9b3
--- /dev/null
+++ b/include/da9030.h
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* DA9030 register definitions */
+#define CID			0x00
+#define EVENT_A			0x01
+#define EVENT_B			0x02
+#define EVENT_C			0x03
+#define STATUS			0x04
+#define IRQ_MASK_A		0x05
+#define IRQ_MASK_B		0x06
+#define IRQ_MASK_C		0x07
+#define SYS_CONTROL_A		0x08
+#define SYS_CONTROL_B		0x09
+#define FAULT_LOG		0x0A
+#define LDO_10_11		0x10
+#define LDO_15			0x11
+#define LDO_14_16		0x12
+#define LDO_18_19		0x13
+#define LDO_17_SIMCP0		0x14
+#define BUCK2_DVC1		0x15
+#define BUCK2_DVC2		0x16
+#define REG_CONTROL_1_17	0x17
+#define REG_CONTROL_2_18	0x18
+#define USBPUMP			0x19
+#define SLEEP_CONTROL		0x1A
+#define STARTUP_CONTROL		0x1B
+#define LED1_CONTROL		0x20
+#define LED2_CONTROL		0x21
+#define LED3_CONTROL		0x22
+#define LED4_CONTROL		0x23
+#define LEDPC_CONTROL		0x24
+#define WLED_CONTROL		0x25
+#define MISC_CONTROLA		0x26
+#define MISC_CONTROLB		0x27
+#define CHARGE_CONTROL		0x28
+#define CCTR_CONTROL		0x29
+#define TCTR_CONTROL		0x2A
+#define CHARGE_PULSE		0x2B
+
+/* ... some missing ...*/
+
+#define LDO1			0x90
+#define LDO2_3			0x91
+#define LDO4_5			0x92
+#define LDO6_SIMCP		0x93
+#define LDO7_8			0x94
+#define LDO9_12			0x95
+#define BUCK			0x96
+#define REG_CONTROL_1_97	0x97
+#define REG_CONTROL_2_98	0x98
+#define REG_SLEEP_CONTROL1	0x99
+#define REG_SLEEP_CONTROL2	0x9A
+#define REG_SLEEP_CONTROL3	0x9B
+#define ADC_MAN_CONTROL		0xA0
+#define ADC_AUTO_CONTROL	0xA1
+#define VBATMON			0xA2
+#define VBATMONTXMON		0xA3
+#define TBATHIGHP		0xA4
+#define TBATHIGHN		0xA5
+#define TBATLOW			0xA6
+#define MAN_RES			0xB0
+#define VBAT_RES		0xB1
+#define VBATMIN_RES		0xB2
+#define VBATMINTXON_RES		0xB3
+#define ICHMAX_RES		0xB4
+#define ICHMIN_RES		0xB5
+#define ICHAVERAGE_RES		0xB6
+#define VCHMAX_RES		0xB7
+#define VCHMIN_RES		0xB8
+#define TBAT_RES		0xB9
+#define ADC_IN4_RES		0xBA
+
+#define STATUS_ONKEY_N		0x1	/* current ONKEY_N value */
+#define STATUS_PWREN1		(1<<1)	/* PWREN1 value */
+#define STATUS_EXTON		(1<<2)	/* EXTON value */
+#define STATUS_CHDET		(1<<3)	/* Charger detection status */
+#define STATUS_TBAT		(1<<4)	/* Battery over/under temperature status */
+#define STATUS_VBATMON		(1<<5)	/* VBATMON comparison status */
+#define STATUS_VBATMONTXON	(1<<6)	/* VBATMONTXON comparison status */
+#define STATUS_CHIOVER		(1<<7)	/* Charge overcurrent */
+
+#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE	0x1
+#define SYS_CONTROL_A_SHUT_DOWN			(1<<1)
+#define SYS_CONTROL_A_HWRES_ENABLE		(1<<2)
+#define SYS_CONTROL_A_WDOG_ACTION		(1<<3)
+#define SYS_CONTROL_A_WATCHDOG			(1<<7)