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-rw-r--r--cpu/mpc512x/Makefile18
-rw-r--r--cpu/mpc512x/asm-offsets.h15
-rw-r--r--cpu/mpc512x/config.mk6
-rw-r--r--cpu/mpc512x/cpu.c1
-rw-r--r--cpu/mpc512x/cpu_init.c27
-rw-r--r--cpu/mpc512x/diu.c189
-rw-r--r--cpu/mpc512x/i2c.c73
-rw-r--r--cpu/mpc512x/ide.c128
-rw-r--r--cpu/mpc512x/iim.c4
-rw-r--r--cpu/mpc512x/iopin.c10
-rw-r--r--cpu/mpc512x/pci.c227
-rw-r--r--cpu/mpc512x/serial.c92
-rw-r--r--cpu/mpc512x/speed.c26
-rw-r--r--cpu/mpc512x/start.S6
-rw-r--r--cpu/mpc512x/u-boot.lds121
15 files changed, 816 insertions, 127 deletions
diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile
index 297d13584..022c676de 100644
--- a/cpu/mpc512x/Makefile
+++ b/cpu/mpc512x/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2007 DENX Software Engineering
+# (C) Copyright 2007-2009 DENX Software Engineering
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -22,14 +22,20 @@
include $(TOPDIR)/config.mk
+$(shell mkdir -p $(OBJTREE)/board/freescale/common)
+
LIB = $(obj)lib$(CPU).a
START = start.o
-COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
-ifdef CONFIG_IIM
-COBJS += iim.o
-endif
-
+COBJS-y := traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o i2c.o iopin.o
+COBJS-${CONFIG_FSL_DIU_FB} += diu.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_diu_fb.o
+COBJS-${CONFIG_FSL_DIU_FB} += ../../board/freescale/common/fsl_logo_bmp.o
+COBJS-${CONFIG_CMD_IDE} += ide.o
+COBJS-${CONFIG_IIM} += iim.o
+COBJS-$(CONFIG_PCI) += pci.o
+
+COBJS := $(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
START := $(addprefix $(obj),$(START))
diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h
new file mode 100644
index 000000000..4b147783f
--- /dev/null
+++ b/cpu/mpc512x/asm-offsets.h
@@ -0,0 +1,15 @@
+/*
+ * needed for cpu/mpc512x/start.S
+ *
+ * These should be auto-generated
+ */
+#define LPCS0AW 0x0024
+#define SRAMBAR 0x00C4
+#define SWCRR 0x0904
+#define LPC_OFFSET 0x10000
+#define CS0_CONFIG 0x00000
+#define CS_CTRL 0x00020
+#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
+
+#define EXC_OFF_SYS_RESET 0x0100
+#define _START_OFFSET EXC_OFF_SYS_RESET
diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk
index 5b7e1f268..6ab34b198 100644
--- a/cpu/mpc512x/config.mk
+++ b/cpu/mpc512x/config.mk
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2007 DENX Software Engineering
+# (C) Copyright 2007-2009 DENX Software Engineering
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -23,3 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \
-ffixed-r2 -msoft-float -mcpu=603e
+
+# Use default linker script.
+# A board port can override this setting in board/*/config.mk
+LDSCRIPT := $(SRCTREE)/cpu/mpc512x/u-boot.lds
diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c
index 8021bc15e..42ccd81e7 100644
--- a/cpu/mpc512x/cpu.c
+++ b/cpu/mpc512x/cpu.c
@@ -29,7 +29,6 @@
#include <common.h>
#include <command.h>
-#include <mpc512x.h>
#include <net.h>
#include <netdev.h>
#include <asm/processor.h>
diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c
index fa753c8e7..fe6beaf84 100644
--- a/cpu/mpc512x/cpu_init.c
+++ b/cpu/mpc512x/cpu_init.c
@@ -1,6 +1,6 @@
/*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- * (C) Copyright 2007 DENX Software Engineering
+ * Copyright (C) 2007-2009 DENX Software Engineering
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -25,7 +25,8 @@
*/
#include <common.h>
-#include <mpc512x.h>
+#include <asm/io.h>
+#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -46,30 +47,34 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_SYS_ACR_PIPE_DEP
/* Arbiter pipeline depth */
- im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
- (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
+ out_be32(&im->arbiter.acr,
+ (im->arbiter.acr & ~ACR_PIPE_DEP) |
+ (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
+ );
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT
/* Arbiter repeat count */
- im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) |
- (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT));
+ out_be32(im->arbiter.acr,
+ (im->arbiter.acr & ~(ACR_RPTCNT)) |
+ (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
+ );
#endif
/* RSR - Reset Status Register - clear all status */
gd->reset_status = im->reset.rsr;
- im->reset.rsr = ~(RSR_RES);
+ out_be32(&im->reset.rsr, ~RSR_RES);
/*
* RMR - Reset Mode Register - enable checkstop reset
*/
- im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT));
+ out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
/* Set IPS-CSB divider: IPS = 1/2 CSB */
- ips_div = im->clk.scfr[0];
+ ips_div = in_be32(&im->clk.scfr[0]);
ips_div &= ~(SCFR1_IPS_DIV_MASK);
ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
- im->clk.scfr[0] = ips_div;
+ out_be32(&im->clk.scfr[0], ips_div);
/*
* Enable Time Base/Decrementer
@@ -78,7 +83,7 @@ void cpu_init_f (volatile immap_t * im)
* have udelay() working; if not enabled, usually leads to a hang, like
* during FLASH chip identification etc.
*/
- im->sysconf.spcr |= SPCR_TBEN;
+ setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
}
int cpu_init_r (void)
diff --git a/cpu/mpc512x/diu.c b/cpu/mpc512x/diu.c
new file mode 100644
index 000000000..70849ee21
--- /dev/null
+++ b/cpu/mpc512x/diu.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ * York Sun <yorksun@freescale.com>
+ *
+ * FSL DIU Framebuffer driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+
+#include "../../board/freescale/common/pixis.h"
+#include "../../board/freescale/common/fsl_diu_fb.h"
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+#include <devices.h>
+#include <video_fb.h>
+#endif
+
+#ifdef CONFIG_FSL_DIU_LOGO_BMP
+extern unsigned int FSL_Logo_BMP[];
+#else
+#define FSL_Logo_BMP NULL
+#endif
+
+static int xres, yres;
+
+void diu_set_pixel_clock(unsigned int pixclock)
+{
+ volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
+ volatile clk512x_t *clk = &immap->clk;
+ volatile unsigned int *clkdvdr = &clk->scfr[0];
+ unsigned long speed_ccb, temp, pixval;
+
+ speed_ccb = get_bus_freq(0) * 4;
+ temp = 1000000000/pixclock;
+ temp *= 1000;
+ pixval = speed_ccb / temp;
+ debug("DIU pixval = %lu\n", pixval);
+
+ /* Modify PXCLK in GUTS CLKDVDR */
+ debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
+ temp = *clkdvdr & 0xFFFFFF00;
+ *clkdvdr = temp | (pixval & 0xFF);
+ debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
+}
+
+char *valid_bmp(char *addr)
+{
+ unsigned long h_addr;
+
+ h_addr = simple_strtoul(addr, NULL, 16);
+ if (h_addr < CONFIG_SYS_FLASH_BASE ||
+ h_addr >= (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - 1)) {
+ printf("bmp addr %lx is not a valid flash address\n", h_addr);
+ return 0;
+ } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) {
+ printf("bmp addr is not a bmp\n");
+ return 0;
+ } else
+ return (char *)h_addr;
+}
+
+int mpc5121_diu_init(void)
+{
+ unsigned int pixel_format;
+ char *bmp = NULL;
+ char *bmp_env;
+
+ xres = 1024;
+ yres = 768;
+ pixel_format = 0x88883316;
+
+ debug("mpc5121_diu_init\n");
+ bmp_env = getenv("diu_bmp_addr");
+ if (bmp_env) {
+ bmp = valid_bmp(bmp_env);
+ }
+ if (!bmp)
+ bmp = (char *)FSL_Logo_BMP;
+ return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp);
+}
+
+int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp,
+ int flag, int argc, char *argv[])
+{
+ unsigned int addr;
+
+ if (argc < 2) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ if (!strncmp(argv[1], "init", 4)) {
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+ fsl_diu_clear_screen();
+ drv_video_init();
+#else
+ return mpc5121_diu_init();
+#endif
+ } else {
+ addr = simple_strtoul(argv[1], NULL, 16);
+ fsl_diu_clear_screen();
+ fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp,
+ "Init or Display BMP file",
+ "init\n - initialize DIU\n"
+ "addr\n - display bmp at address 'addr'"
+ );
+
+
+#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)
+
+/*
+ * The Graphic Device
+ */
+GraphicDevice ctfb;
+void *video_hw_init(void)
+{
+ GraphicDevice *pGD = (GraphicDevice *) &ctfb;
+ struct fb_info *info;
+
+ if (mpc5121_diu_init() < 0)
+ return;
+
+ /* fill in Graphic device struct */
+ sprintf(pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz",
+ xres, yres, 32, 64, 60);
+
+ pGD->frameAdrs = (unsigned int)fsl_fb_open(&info);
+ pGD->winSizeX = xres;
+ pGD->winSizeY = yres - info->logo_height;
+ pGD->plnSizeX = pGD->winSizeX;
+ pGD->plnSizeY = pGD->winSizeY;
+
+ pGD->gdfBytesPP = 4;
+ pGD->gdfIndex = GDF_32BIT_X888RGB;
+
+ pGD->isaBase = 0;
+ pGD->pciBase = 0;
+ pGD->memSize = info->screen_size - info->logo_size;
+
+ /* Cursor Start Address */
+ pGD->dprBase = 0;
+ pGD->vprBase = 0;
+ pGD->cprBase = 0;
+
+ return (void *)pGD;
+}
+
+/**
+ * Set the LUT
+ *
+ * @index: color number
+ * @r: red
+ * @b: blue
+ * @g: green
+ */
+void video_set_lut
+ (unsigned int index, unsigned char r, unsigned char g, unsigned char b)
+{
+ return;
+}
+
+#endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */
diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c
index 4f6bc8640..e2d909751 100644
--- a/cpu/mpc512x/i2c.c
+++ b/cpu/mpc512x/i2c.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2003 - 2007
+ * (C) Copyright 2003 - 2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -24,18 +24,16 @@
*/
#include <common.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_HARD_I2C
-#include <mpc512x.h>
#include <i2c.h>
-#define immr ((immap_t *)CONFIG_SYS_IMMR)
-
/* by default set I2C bus 0 active */
-static unsigned int bus_num = 0;
+static unsigned int bus_num __attribute__ ((section (".data"))) = 0;
#define I2C_TIMEOUT 100
#define I2C_RETRIES 3
@@ -56,29 +54,24 @@ static int mpc_get_fdr(int);
static int mpc_reg_in (volatile u32 *reg)
{
- int ret = *reg >> 24;
- __asm__ __volatile__ ("eieio");
+ int ret = in_be32(reg) >> 24;
+
return ret;
}
static void mpc_reg_out (volatile u32 *reg, int val, int mask)
{
- int tmp;
-
if (!mask) {
- *reg = val << 24;
+ out_be32(reg, val << 24);
} else {
- tmp = mpc_reg_in (reg);
- *reg = ((tmp & ~mask) | (val & mask)) << 24;
+ clrsetbits_be32(reg, mask << 24, (val & mask) << 24);
}
- __asm__ __volatile__ ("eieio");
-
- return;
}
static int wait_for_bb (void)
{
- i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int timeout = I2C_TIMEOUT;
int status;
@@ -101,7 +94,8 @@ static int wait_for_bb (void)
static int wait_for_pin (int *status)
{
- i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int timeout = I2C_TIMEOUT;
*status = mpc_reg_in (&regs->msr);
@@ -122,7 +116,8 @@ static int wait_for_pin (int *status)
static int do_address (uchar chip, char rdwr_flag)
{
- i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int status;
chip <<= 1;
@@ -147,7 +142,8 @@ static int do_address (uchar chip, char rdwr_flag)
static int send_bytes (uchar chip, char *buf, int len)
{
- i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int wrcount;
int status;
@@ -170,7 +166,8 @@ static int send_bytes (uchar chip, char *buf, int len)
static int receive_bytes (uchar chip, char *buf, int len)
{
- i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int dummy = 1;
int rdcount = 0;
int status;
@@ -208,9 +205,12 @@ static int receive_bytes (uchar chip, char *buf, int len)
void i2c_init (int speed, int saddr)
{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
int i;
- for(i = 0; i < I2C_BUS_CNT; i++){
- i2c512x_dev_t *regs = &immr->i2c.dev[i];
+
+ for (i = 0; i < I2C_BUS_CNT; i++){
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[i];
+
mpc_reg_out (&regs->mcr, 0, 0);
/* Set clock */
@@ -223,10 +223,10 @@ void i2c_init (int speed, int saddr)
}
/* Disable interrupts */
- immr->i2c.icr = 0;
+ out_be32(&im->i2c.icr, 0);
+
/* Turn off filters */
- immr->i2c.mifr = 0;
- return;
+ out_be32(&im->i2c.mifr, 0);
}
static int mpc_get_fdr (int speed)
@@ -281,7 +281,8 @@ static int mpc_get_fdr (int speed)
int i2c_probe (uchar chip)
{
- i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
int i;
for (i = 0; i < I2C_RETRIES; i++) {
@@ -302,8 +303,9 @@ int i2c_probe (uchar chip)
int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len)
{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
char xaddr[4];
- i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int ret = -1;
xaddr[0] = (addr >> 24) & 0xFF;
@@ -346,8 +348,9 @@ Done:
int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len)
{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile i2c512x_dev_t *regs = &im->i2c.dev[bus_num];
char xaddr[4];
- i2c512x_dev_t *regs = &immr->i2c.dev[bus_num];
int ret = -1;
xaddr[0] = (addr >> 24) & 0xFF;
@@ -397,18 +400,4 @@ unsigned int i2c_get_bus_num (void)
return bus_num;
}
-/* TODO */
-unsigned int i2c_get_bus_speed (void)
-{
- return -1;
-}
-
-int i2c_set_bus_speed (unsigned int speed)
-{
- if (speed != CONFIG_SYS_I2C_SPEED)
- return -1;
-
- return 0;
-}
-
#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/mpc512x/ide.c b/cpu/mpc512x/ide.c
new file mode 100644
index 000000000..dd6b2f467
--- /dev/null
+++ b/cpu/mpc512x/ide.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_IDE_RESET)
+
+void ide_set_reset (int idereset)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ debug ("ide_set_reset(%d)\n", idereset);
+
+ if (idereset) {
+ out_be32(&im->pata.pata_ata_control, 0);
+ } else {
+ out_be32(&im->pata.pata_ata_control, FSL_ATA_CTRL_ATA_RST_B);
+ }
+ udelay(100);
+}
+
+void init_ide_reset (void)
+{
+ debug ("init_ide_reset\n");
+
+ /*
+ * Clear the reset bit to reset the interface
+ * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
+ */
+ ide_set_reset(1);
+
+ /* Assert the reset bit to enable the interface */
+ ide_set_reset(0);
+
+}
+
+#define CALC_TIMING(t) (t + period - 1) / period
+
+int ide_preinit (void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ long t;
+ const struct {
+ short t0;
+ short t1;
+ short t2_8;
+ short t2_16;
+ short t2i;
+ short t4;
+ short t9;
+ short tA;
+ } pio_specs = {
+ .t0 = 600,
+ .t1 = 70,
+ .t2_8 = 290,
+ .t2_16 = 165,
+ .t2i = 0,
+ .t4 = 30,
+ .t9 = 20,
+ .tA = 50,
+ };
+ union {
+ u32 config;
+ struct {
+ u8 field1;
+ u8 field2;
+ u8 field3;
+ u8 field4;
+ }bytes;
+ } cfg;
+
+ debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
+ (u32)&im->pata);
+
+ /* Set the reset bit to 1 to enable the interface */
+ ide_set_reset(0);
+
+ /* Init timings : we use PIO mode 0 timings */
+ t = 1000000000 / gd->ips_clk; /* period in ns */
+ cfg.bytes.field1 = 3;
+ cfg.bytes.field2 = 3;
+ cfg.bytes.field3 = (pio_specs.t1 + t) / t;
+ cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
+
+ out_be32(&im->pata.pata_time1, cfg.config);
+
+ cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
+ cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
+ cfg.bytes.field3 = 1;
+ cfg.bytes.field4 = (pio_specs.t4 + t) / t;
+
+ out_be32(&im->pata.pata_time2, cfg.config);
+
+ cfg.config = in_be32(&im->pata.pata_time3);
+ cfg.bytes.field1 = (pio_specs.t9 + t) / t;
+
+ out_be32(&im->pata.pata_time3, cfg.config);
+
+ debug ("PATA preinit complete.\n");
+
+ return 0;
+}
+
+#endif /* defined(CONFIG_IDE_RESET) */
diff --git a/cpu/mpc512x/iim.c b/cpu/mpc512x/iim.c
index 6cdc42259..8f2eb37e1 100644
--- a/cpu/mpc512x/iim.c
+++ b/cpu/mpc512x/iim.c
@@ -389,6 +389,6 @@ U_BOOT_CMD(
" no args for entire bank\n"
"fuse prog <frow_bit> - program fuse at row <frow>, bit <_bit>\n"
" <frow> is 0-31, <bit> is 0-7; eg. 13_2 \n"
- " WARNING - this is permanent\n"
- );
+ " WARNING - this is permanent"
+);
#endif /* CONFIG_CMD_FUSE */
diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c
index 78f4fa1e8..be2094762 100644
--- a/cpu/mpc512x/iopin.c
+++ b/cpu/mpc512x/iopin.c
@@ -23,15 +23,15 @@
#include <common.h>
#include <linux/types.h>
-#include <mpc512x.h>
+#include <asm/io.h>
void iopin_initialize(iopin_t *ioregs_init, int len)
{
short i, j, p;
- u_long *reg;
+ u32 *reg;
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
- reg = (u_long *)&(im->io_ctrl.regs[0]);
+ reg = (u32 *)&(im->io_ctrl);
if (sizeof(ioregs_init) == 0)
return;
@@ -40,9 +40,9 @@ void iopin_initialize(iopin_t *ioregs_init, int len)
for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
p < ioregs_init[i].nr_pins; p++, j++) {
if (ioregs_init[i].bit_or)
- reg[j] |= ioregs_init[i].val;
+ setbits_be32(reg + j, ioregs_init[i].val);
else
- reg[j] = ioregs_init[i].val;
+ out_be32 (reg + j, ioregs_init[i].val);
}
}
return;
diff --git a/cpu/mpc512x/pci.c b/cpu/mpc512x/pci.c
new file mode 100644
index 000000000..166a993c2
--- /dev/null
+++ b/cpu/mpc512x/pci.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006, 2007. All rights reserved.
+ * Copyright (C) 2009 DENX Software Engineering <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <asm/global_data.h>
+#include <pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* System RAM mapped to PCI space */
+#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
+
+static struct pci_controller pci_hose;
+
+
+/**************************************************************************
+ * pci_init_board()
+ *
+ */
+void
+pci_init_board(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile law512x_t *pci_law;
+ volatile pot512x_t *pci_pot;
+ volatile pcictrl512x_t *pci_ctrl;
+ volatile pciconf512x_t *pci_conf;
+ u16 reg16;
+ u32 reg32;
+ u32 dev;
+ int i;
+ struct pci_controller *hose;
+
+ /* Set PCI divider for 33MHz */
+ reg32 = im->clk.scfr[0];
+ reg32 &= ~(SCFR1_PCI_DIV_MASK);
+ reg32 |= SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT;
+ im->clk.scfr[0] = reg32;
+
+ clrsetbits_be32(&im->clk.scfr[0],
+ SCFR1_PCI_DIV_MASK,
+ SCFR1_PCI_DIV << SCFR1_PCI_DIV_SHIFT
+ );
+
+ pci_law = im->sysconf.pcilaw;
+ pci_pot = im->ios.pot;
+ pci_ctrl = &im->pci_ctrl;
+ pci_conf = &im->pci_conf;
+
+ hose = &pci_hose;
+
+ /*
+ * Release PCI RST Output signal
+ */
+ out_be32(&pci_ctrl->gcr, 0);
+ udelay(2000);
+ out_be32(&pci_ctrl->gcr, 1);
+
+ /* We need to wait at least a 1sec based on PCI specs */
+ for (i = 0; i < 1000; i++)
+ udelay(1000);
+
+ /*
+ * Configure PCI Local Access Windows
+ */
+ out_be32(&pci_law[0].bar, CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR);
+ out_be32(&pci_law[0].ar, LAWAR_EN | LAWAR_SIZE_512M);
+
+ out_be32(&pci_law[1].bar, CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR);
+ out_be32(&pci_law[1].ar, LAWAR_EN | LAWAR_SIZE_16M);
+
+ /*
+ * Configure PCI Outbound Translation Windows
+ */
+
+ /* PCI mem space - prefetch */
+ out_be32(&pci_pot[0].potar,
+ (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK);
+ out_be32(&pci_pot[0].pobar,
+ (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK);
+ out_be32(&pci_pot[0].pocmr,
+ POCMR_EN | POCMR_PRE | POCMR_CM_256M);
+
+ /* PCI IO space */
+ out_be32(&pci_pot[1].potar,
+ (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK);
+ out_be32(&pci_pot[1].pobar,
+ (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK);
+ out_be32(&pci_pot[1].pocmr,
+ POCMR_EN | POCMR_IO | POCMR_CM_16M);
+
+ /* PCI mmio - non-prefetch mem space */
+ out_be32(&pci_pot[2].potar,
+ (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK);
+ out_be32(&pci_pot[2].pobar,
+ (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK);
+ out_be32(&pci_pot[2].pocmr,
+ POCMR_EN | POCMR_CM_256M);
+
+ /*
+ * Configure PCI Inbound Translation Windows
+ */
+
+ /* we need RAM mapped to PCI space for the devices to
+ * access main memory */
+ out_be32(&pci_ctrl[0].pitar1, 0x0);
+ out_be32(&pci_ctrl[0].pibar1, 0x0);
+ out_be32(&pci_ctrl[0].piebar1, 0x0);
+ out_be32(&pci_ctrl[0].piwar1,
+ PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
+ PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1));
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ /* PCI memory prefetch space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_SYS_PCI_MEM_BASE,
+ CONFIG_SYS_PCI_MEM_PHYS,
+ CONFIG_SYS_PCI_MEM_SIZE,
+ PCI_REGION_MEM|PCI_REGION_PREFETCH);
+
+ /* PCI memory space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_SYS_PCI_MMIO_BASE,
+ CONFIG_SYS_PCI_MMIO_PHYS,
+ CONFIG_SYS_PCI_MMIO_SIZE,
+ PCI_REGION_MEM);
+
+ /* PCI IO space */
+ pci_set_region(hose->regions + 2,
+ CONFIG_SYS_PCI_IO_BASE,
+ CONFIG_SYS_PCI_IO_PHYS,
+ CONFIG_SYS_PCI_IO_SIZE,
+ PCI_REGION_IO);
+
+ /* System memory space */
+ pci_set_region(hose->regions + 3,
+ CONFIG_PCI_SYS_MEM_BUS,
+ CONFIG_PCI_SYS_MEM_PHYS,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ hose->region_count = 4;
+
+ pci_setup_indirect(hose,
+ (CONFIG_SYS_IMMR + 0x8300),
+ (CONFIG_SYS_IMMR + 0x8304));
+
+ pci_register_hose(hose);
+
+ /*
+ * Write to Command register
+ */
+ reg16 = 0xff;
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
+
+ /*
+ * Clear non-reserved bits in status register.
+ */
+ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+
+#ifdef CONFIG_PCI_SCAN_SHOW
+ printf("PCI: Bus Dev VenId DevId Class Int\n");
+#endif
+ /*
+ * Hose scan.
+ */
+ hose->last_busno = pci_hose_scan(hose);
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+ int nodeoffset;
+ int tmp[2];
+ const char *path;
+
+ nodeoffset = fdt_path_offset(blob, "/aliases");
+ if (nodeoffset >= 0) {
+ path = fdt_getprop(blob, nodeoffset, "pci", NULL);
+ if (path) {
+ tmp[0] = cpu_to_be32(pci_hose.first_busno);
+ tmp[1] = cpu_to_be32(pci_hose.last_busno);
+ do_fixup_by_path(blob, path, "bus-range",
+ &tmp, sizeof(tmp), 1);
+
+ tmp[0] = cpu_to_be32(gd->pci_clk);
+ do_fixup_by_path(blob, path, "clock-frequency",
+ &tmp, sizeof(tmp[0]), 1);
+ }
+ }
+}
+#endif /* CONFIG_OF_LIBFDT */
diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c
index 7db87a80a..4fc4693a6 100644
--- a/cpu/mpc512x/serial.c
+++ b/cpu/mpc512x/serial.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000 - 2007
+ * (C) Copyright 2000 - 2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -30,6 +30,8 @@
*/
#include <common.h>
+#include <asm/io.h>
+#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -40,66 +42,73 @@ static void fifo_init (volatile psc512x_t *psc)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
/* reset Rx & Tx fifo slice */
- psc->rfcmd = PSC_FIFO_RESET_SLICE;
- psc->tfcmd = PSC_FIFO_RESET_SLICE;
+ out_be32(&psc->rfcmd, PSC_FIFO_RESET_SLICE);
+ out_be32(&psc->tfcmd, PSC_FIFO_RESET_SLICE);
/* disable Tx & Rx FIFO interrupts */
- psc->rfintmask = 0;
- psc->tfintmask = 0;
+ out_be32(&psc->rfintmask, 0);
+ out_be32(&psc->tfintmask, 0);
- psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
- psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
+ out_be32(&psc->tfsize, CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16));
+ out_be32(&psc->rfsize, CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16));
/* enable Tx & Rx FIFO slice */
- psc->rfcmd = PSC_FIFO_ENABLE_SLICE;
- psc->tfcmd = PSC_FIFO_ENABLE_SLICE;
+ out_be32(&psc->rfcmd, PSC_FIFO_ENABLE_SLICE);
+ out_be32(&psc->tfcmd, PSC_FIFO_ENABLE_SLICE);
- im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE;
+ out_be32(&im->fifoc.fifoc_cmd, FIFOC_DISABLE_CLOCK_GATE);
__asm__ volatile ("sync");
}
+void serial_setbrg(void)
+{
+ volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+ volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
+ unsigned long baseclk, div;
+
+ /* calculate dividor for setting PSC CTUR and CTLR registers */
+ baseclk = (gd->ips_clk + 8) / 16;
+ div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
+
+ out_8(&psc->ctur, (div >> 8) & 0xff);
+ out_8(&psc->ctlr, div & 0xff); /* set baudrate */
+}
+
int serial_init(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
- unsigned long baseclk;
- int div;
fifo_init (psc);
/* set MR register to point to MR1 */
- psc->command = PSC_SEL_MODE_REG_1;
+ out_8(&psc->command, PSC_SEL_MODE_REG_1);
/* disable Tx/Rx */
- psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE;
+ out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
/* choose the prescaler by 16 for the Tx/Rx clock generation */
- psc->psc_clock_select = 0xdd00;
+ out_be16(&psc->psc_clock_select, 0xdd00);
/* switch to UART mode */
- psc->sicr = 0;
+ out_be32(&psc->sicr, 0);
/* mode register points to mr1 */
/* configure parity, bit length and so on in mode register 1*/
- psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
+ out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
/* now, mode register points to mr2 */
- psc->mode = PSC_MODE_1_STOPBIT;
-
- /* calculate dividor for setting PSC CTUR and CTLR registers */
- baseclk = (gd->ips_clk + 8) / 16;
- div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
+ out_8(&psc->mode, PSC_MODE_1_STOPBIT);
- psc->ctur = (div >> 8) & 0xff;
/* set baudrate */
- psc->ctlr = div & 0xff;
+ serial_setbrg();
/* disable all interrupts */
- psc->psc_imr = 0;
+ out_be16(&psc->psc_imr, 0);
/* reset and enable Rx/Tx */
- psc->command = PSC_RST_RX;
- psc->command = PSC_RST_TX;
- psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
+ out_8(&psc->command, PSC_RST_RX);
+ out_8(&psc->command, PSC_RST_TX);
+ out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
return 0;
}
@@ -113,7 +122,7 @@ void serial_putc (const char c)
serial_putc ('\r');
/* Wait for last character to go. */
- while (!(psc->psc_status & PSC_SR_TXEMP))
+ while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
;
psc->tfdata_8 = c;
@@ -125,7 +134,7 @@ void serial_putc_raw (const char c)
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
/* Wait for last character to go. */
- while (!(psc->psc_status & PSC_SR_TXEMP))
+ while (!(in_be16(&psc->psc_status) & PSC_SR_TXEMP))
;
psc->tfdata_8 = c;
@@ -145,7 +154,7 @@ int serial_getc (void)
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
/* Wait for a character to arrive. */
- while (psc->rfstat & PSC_FIFO_EMPTY)
+ while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY)
;
return psc->rfdata_8;
@@ -156,20 +165,7 @@ int serial_tstc (void)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
- return !(psc->rfstat & PSC_FIFO_EMPTY);
-}
-
-void serial_setbrg (void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
- unsigned long baseclk, div;
-
- baseclk = (gd->csb_clk + 8) / 16;
- div = (baseclk + (gd->baudrate / 2)) / gd->baudrate;
-
- psc->ctur = (div >> 8) & 0xFF;
- psc->ctlr = div & 0xff; /* set baudrate */
+ return !(in_be32(&psc->rfstat) & PSC_FIFO_EMPTY);
}
void serial_setrts(int s)
@@ -179,11 +175,11 @@ void serial_setrts(int s)
if (s) {
/* Assert RTS (become LOW) */
- psc->op1 = 0x1;
+ out_8(&psc->op1, 0x1);
}
else {
/* Negate RTS (become HIGH) */
- psc->op0 = 0x1;
+ out_8(&psc->op0, 0x1);
}
}
@@ -192,6 +188,6 @@ int serial_getcts(void)
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
- return (psc->ip & 0x1) ? 0 : 1;
+ return (in_8(&psc->ip) & 0x1) ? 0 : 1;
}
#endif /* CONFIG_PSC_CONSOLE */
diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
index 5992111c1..ce8d0949b 100644
--- a/cpu/mpc512x/speed.c
+++ b/cpu/mpc512x/speed.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2007
+ * (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
@@ -26,8 +26,8 @@
*/
#include <common.h>
-#include <mpc512x.h>
#include <command.h>
+#include <asm/io.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -75,29 +75,37 @@ int get_clocks (void)
u32 csb_clk;
u32 ips_clk;
u32 pci_clk;
+ u32 reg;
- if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
+ reg = in_be32(&im->sysconf.immrbar);
+ if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
- spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
+ reg = in_be32(&im->clk.spmr);
+ spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
spll = ref_clk * spmf_mult[spmf];
- sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
+ reg = in_be32(&im->clk.scfr[1]);
+ sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
csb_clk = sys_clk / 2;
- cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
+ reg = in_be32(&im->clk.spmr);
+ cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
- ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
+ reg = in_be32(&im->clk.scfr[0]);
+ ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
if (ips_div != 0) {
ips_clk = csb_clk / ips_div;
} else {
/* in case we cannot get a sane IPS divisor, fail gracefully */
ips_clk = 0;
}
- pci_div = (im->clk.scfr[0] & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
+
+ reg = in_be32(&im->clk.scfr[0]);
+ pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
if (pci_div != 0) {
pci_clk = csb_clk / pci_div;
} else {
@@ -138,7 +146,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(clocks, 1, 0, do_clocks,
"print clock configuration",
- " clocks\n"
+ " clocks"
);
int prt_mpc512x_clks (void)
diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S
index 360682daf..178e5d1b3 100644
--- a/cpu/mpc512x/start.S
+++ b/cpu/mpc512x/start.S
@@ -1,7 +1,7 @@
/*
* Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
* Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
* Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
*
* See file CREDITS for list of people who contributed to this
@@ -30,12 +30,14 @@
*/
#include <config.h>
-#include <mpc512x.h>
#include <timestamp.h>
#include <version.h>
#define CONFIG_521X 1 /* needed for Linux kernel header files*/
+#include <asm/immap_512x.h>
+#include "asm-offsets.h"
+
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
diff --git a/cpu/mpc512x/u-boot.lds b/cpu/mpc512x/u-boot.lds
new file mode 100644
index 000000000..dae32697e
--- /dev/null
+++ b/cpu/mpc512x/u-boot.lds
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc512x/start.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ . = ALIGN(16);
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+ENTRY(_start)
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-27 21:17:45 +0000