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-rw-r--r--cpu/pxa/Makefile43
-rw-r--r--cpu/pxa/config.mk28
-rw-r--r--cpu/pxa/cpu.c152
-rw-r--r--cpu/pxa/i2c.c460
-rw-r--r--cpu/pxa/interrupts.c205
-rw-r--r--cpu/pxa/serial.c166
-rw-r--r--cpu/pxa/start.S474
7 files changed, 1528 insertions, 0 deletions
diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile
new file mode 100644
index 000000000..778a6646f
--- /dev/null
+++ b/cpu/pxa/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o
+OBJS = serial.o interrupts.o cpu.o i2c.o
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk
new file mode 100644
index 000000000..c40dcf861
--- /dev/null
+++ b/cpu/pxa/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2002
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
+ -mshort-load-bytes -msoft-float
+
+PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=strongarm1100
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
new file mode 100644
index 000000000..6a3c24ded
--- /dev/null
+++ b/cpu/pxa/cpu.c
@@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+
+int cpu_init (void)
+{
+ /*
+ * setup up stack if necessary
+ */
+/*
+
+ FIXME: the stack is _below_ the uboot code!!
+
+#ifdef CONFIG_USE_IRQ
+ IRQ_STACK_START = _armboot_end +
+ CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4;
+ FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ;
+ _armboot_real_end = FIQ_STACK_START + 4;
+#else
+ _armboot_real_end = _armboot_end + CONFIG_STACKSIZE;
+#endif
+*/
+ return (0);
+}
+
+int cleanup_before_linux (void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * just disable everything that can disturb booting linux
+ */
+
+ unsigned long i;
+
+ disable_interrupts ();
+
+ /* turn off I-cache */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ i &= ~0x1000;
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+ /* flush I-cache */
+ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+
+ return (0);
+}
+
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ extern void reset_cpu (ulong addr);
+
+ printf ("reseting ...\n");
+
+ udelay (50000); /* wait 50 ms */
+ disable_interrupts ();
+ reset_cpu (0);
+
+ /*NOTREACHED*/
+ return (0);
+}
+
+/* taken from blob */
+void icache_enable (void)
+{
+ register u32 i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ /* set i-cache */
+ i |= 0x1000;
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+}
+
+void icache_disable (void)
+{
+ register u32 i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ /* clear i-cache */
+ i &= ~0x1000;
+
+ /* write back to control register */
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+ /* flush i-cache */
+ asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
+}
+
+int icache_status (void)
+{
+ register u32 i;
+
+ /* read control register */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+
+ /* return bit */
+ return (i & 0x1000);
+}
+
+/* we will never enable dcache, because we have to setup MMU first */
+void dcache_enable (void)
+{
+ return;
+}
+
+void dcache_disable (void)
+{
+ return;
+}
+
+int dcache_status (void)
+{
+ return 0; /* always off */
+}
diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c
new file mode 100644
index 000000000..406f825cd
--- /dev/null
+++ b/cpu/pxa/i2c.c
@@ -0,0 +1,460 @@
+/*
+ * (C) Copyright 2000
+ * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
+ *
+ * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2003 Pengutronix e.K.
+ * Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+
+/* FIXME: this file is PXA255 specific! What about other XScales? */
+
+#include <common.h>
+
+#ifdef CONFIG_HARD_I2C
+
+/*
+ * - CFG_I2C_SPEED
+ * - I2C_PXA_SLAVE_ADDR
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/pxa-regs.h>
+#include <i2c.h>
+
+//#define DEBUG_I2C 1 /* activate local debugging output */
+#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */
+#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
+#define I2C_ISR_INIT 0x7FF
+
+#ifdef DEBUG_I2C
+#define PRINTD(x) printf x
+#else
+#define PRINTD(x)
+#endif
+
+
+/* Shall the current transfer have a start/stop condition? */
+#define I2C_COND_NORMAL 0
+#define I2C_COND_START 1
+#define I2C_COND_STOP 2
+
+/* Shall the current transfer be ack/nacked or being waited for it? */
+#define I2C_ACKNAK_WAITACK 1
+#define I2C_ACKNAK_SENDACK 2
+#define I2C_ACKNAK_SENDNAK 4
+
+/* Specify who shall transfer the data (master or slave) */
+#define I2C_READ 0
+#define I2C_WRITE 1
+
+/* All transfers are described by this data structure */
+struct i2c_msg {
+ u8 condition;
+ u8 acknack;
+ u8 direction;
+ u8 data;
+};
+
+
+/**
+ * i2c_pxa_reset: - reset the host controller
+ *
+ */
+
+static void i2c_reset( void )
+{
+ ICR &= ~ICR_IUE; /* disable unit */
+ ICR |= ICR_UR; /* reset the unit */
+ udelay(100);
+ ICR &= ~ICR_IUE; /* disable unit */
+ CKEN |= CKEN14_I2C; /* set the global I2C clock on */
+ ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
+ ICR = I2C_ICR_INIT; /* set control register values */
+ ISR = I2C_ISR_INIT; /* set clear interrupt bits */
+ ICR |= ICR_IUE; /* enable unit */
+ udelay(100);
+}
+
+
+/**
+ * i2c_isr_set_cleared: - wait until certain bits of the I2C status register
+ * are set and cleared
+ *
+ * @return: 0 in case of success, 1 means timeout (no match within 10 ms).
+ */
+
+static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
+{
+ int timeout = 10000;
+
+ while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){
+ udelay( 10 );
+ if( timeout-- < 0 ) return 0;
+ }
+
+ return 1;
+}
+
+
+/**
+ * i2c_transfer: - Transfer one byte over the i2c bus
+ *
+ * This function can tranfer a byte over the i2c bus in both directions.
+ * It is used by the public API functions.
+ *
+ * @return: 0: transfer successful
+ * -1: message is empty
+ * -2: transmit timeout
+ * -3: ACK missing
+ * -4: receive timeout
+ * -5: illegal parameters
+ * -6: bus is busy and couldn't be aquired
+ */
+int i2c_transfer(struct i2c_msg *msg)
+{
+ int ret;
+
+ if (!msg)
+ goto transfer_error_msg_empty;
+
+ switch(msg->direction) {
+
+ case I2C_WRITE:
+
+ /* check if bus is not busy */
+ if (!i2c_isr_set_cleared(0,ISR_IBB))
+ goto transfer_error_bus_busy;
+
+ /* start transmission */
+ ICR &= ~ICR_START;
+ ICR &= ~ICR_STOP;
+ IDBR = msg->data;
+ if (msg->condition == I2C_COND_START) ICR |= ICR_START;
+ if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
+ if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
+ if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
+ ICR &= ~ICR_ALDIE;
+ ICR |= ICR_TB;
+
+ /* transmit register empty? */
+ if (!i2c_isr_set_cleared(ISR_ITE,0))
+ goto transfer_error_transmit_timeout;
+
+ /* clear 'transmit empty' state */
+ ISR |= ISR_ITE;
+
+ /* wait for ACK from slave */
+ if (msg->acknack == I2C_ACKNAK_WAITACK)
+ if (!i2c_isr_set_cleared(0,ISR_ACKNAK))
+ goto transfer_error_ack_missing;
+ break;
+
+ case I2C_READ:
+
+ /* check if bus is not busy */
+ if (!i2c_isr_set_cleared(0,ISR_IBB))
+ goto transfer_error_bus_busy;
+
+ /* start receive */
+ ICR &= ~ICR_START;
+ ICR &= ~ICR_STOP;
+ if (msg->condition == I2C_COND_START) ICR |= ICR_START;
+ if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP;
+ if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK;
+ if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK;
+ ICR &= ~ICR_ALDIE;
+ ICR |= ICR_TB;
+
+ /* receive register full? */
+ if (!i2c_isr_set_cleared(ISR_IRF,0))
+ goto transfer_error_receive_timeout;
+
+ msg->data = IDBR;
+
+ /* clear 'receive empty' state */
+ ISR |= ISR_IRF;
+
+ break;
+
+ default:
+
+ goto transfer_error_illegal_param;
+
+ }
+
+ return 0;
+
+transfer_error_msg_empty:
+ PRINTD(("i2c_transfer: error: 'msg' is empty\n"));
+ ret = -1; goto i2c_transfer_finish;
+
+transfer_error_transmit_timeout:
+ PRINTD(("i2c_transfer: error: transmit timeout\n"));
+ ret = -2; goto i2c_transfer_finish;
+
+transfer_error_ack_missing:
+ PRINTD(("i2c_transfer: error: ACK missing\n"));
+ ret = -3; goto i2c_transfer_finish;
+
+transfer_error_receive_timeout:
+ PRINTD(("i2c_transfer: error: receive timeout\n"));
+ ret = -4; goto i2c_transfer_finish;
+
+transfer_error_illegal_param:
+ PRINTD(("i2c_transfer: error: illegal parameters\n"));
+ ret = -5; goto i2c_transfer_finish;
+
+transfer_error_bus_busy:
+ PRINTD(("i2c_transfer: error: bus is busy\n"));
+ ret = -6; goto i2c_transfer_finish;
+
+i2c_transfer_finish:
+ PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR));
+ i2c_reset();
+ return ret;
+
+}
+
+/* ------------------------------------------------------------------------ */
+/* API Functions */
+/* ------------------------------------------------------------------------ */
+
+void i2c_init(int speed, int slaveaddr)
+{
+#ifdef CFG_I2C_INIT_BOARD
+ /* call board specific i2c bus reset routine before accessing the */
+ /* environment, which might be in a chip on that bus. For details */
+ /* about this problem see doc/I2C_Edge_Conditions. */
+ i2c_init_board();
+#endif
+}
+
+
+/**
+ * i2c_probe: - Test if a chip answers for a given i2c address
+ *
+ * @chip: address of the chip which is searched for
+ * @return: 0 if a chip was found, -1 otherwhise
+ */
+
+int i2c_probe(uchar chip)
+{
+ struct i2c_msg msg;
+
+ i2c_reset();
+
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1) + 1;
+ if (i2c_transfer(&msg)) return -1;
+
+ msg.condition = I2C_COND_STOP;
+ msg.acknack = I2C_ACKNAK_SENDNAK;
+ msg.direction = I2C_READ;
+ msg.data = 0x00;
+ if (i2c_transfer(&msg)) return -1;
+
+ return 0;
+}
+
+
+/**
+ * i2c_read: - Read multiple bytes from an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip: address of the chip which is to be read
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to write the data
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
+ */
+
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ struct i2c_msg msg;
+ u8 addr_bytes[3]; /* lowest...highest byte of data address */
+ int ret;
+
+ PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len));
+
+ i2c_reset();
+
+ /* dummy chip address write */
+ PRINTD(("i2c_read: dummy chip address write\n"));
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data &= 0xFE;
+ if ((ret=i2c_transfer(&msg))) return -1;
+
+ /*
+ * send memory address bytes;
+ * alen defines how much bytes we have to send.
+ */
+ //addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1);
+ addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
+ addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
+ addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
+
+ while (--alen >= 0) {
+
+ PRINTD(("i2c_read: send memory word address byte %1d\n",alen));
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = addr_bytes[alen];
+ if ((ret=i2c_transfer(&msg))) return -1;
+ }
+
+
+ /* start read sequence */
+ PRINTD(("i2c_read: start read sequence\n"));
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data |= 0x01;
+ if ((ret=i2c_transfer(&msg))) return -1;
+
+ /* read bytes; send NACK at last byte */
+ while (len--) {
+
+ if (len==0) {
+ msg.condition = I2C_COND_STOP;
+ msg.acknack = I2C_ACKNAK_SENDNAK;
+ } else {
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_SENDACK;
+ }
+
+ msg.direction = I2C_READ;
+ msg.data = 0x00;
+ if ((ret=i2c_transfer(&msg))) return -1;
+
+ *(buffer++) = msg.data;
+
+ PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
+
+ }
+
+ i2c_reset();
+
+ return 0;
+}
+
+
+/**
+ * i2c_write: - Write multiple bytes to an i2c device
+ *
+ * The higher level routines take into account that this function is only
+ * called with len < page length of the device (see configuration file)
+ *
+ * @chip: address of the chip which is to be written
+ * @addr: i2c data address within the chip
+ * @alen: length of the i2c data address (1..2 bytes)
+ * @buffer: where to find the data to be written
+ * @len: how much byte do we want to read
+ * @return: 0 in case of success
+ */
+
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
+{
+ struct i2c_msg msg;
+ u8 addr_bytes[3]; /* lowest...highest byte of data address */
+
+ PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len));
+
+ i2c_reset();
+
+ /* chip address write */
+ PRINTD(("i2c_write: chip address write\n"));
+ msg.condition = I2C_COND_START;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = (chip << 1);
+ msg.data &= 0xFE;
+ if (i2c_transfer(&msg)) return -1;
+
+ /*
+ * send memory address bytes;
+ * alen defines how much bytes we have to send.
+ */
+ addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF);
+ addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF);
+ addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF);
+
+ while (--alen >= 0) {
+
+ PRINTD(("i2c_write: send memory word address\n"));
+ msg.condition = I2C_COND_NORMAL;
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = addr_bytes[alen];
+ if (i2c_transfer(&msg)) return -1;
+ }
+
+ /* write bytes; send NACK at last byte */
+ while (len--) {
+
+ PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
+
+ if (len==0)
+ msg.condition = I2C_COND_STOP;
+ else
+ msg.condition = I2C_COND_NORMAL;
+
+ msg.acknack = I2C_ACKNAK_WAITACK;
+ msg.direction = I2C_WRITE;
+ msg.data = *(buffer++);
+
+ if (i2c_transfer(&msg)) return -1;
+
+ }
+
+ i2c_reset();
+
+ return 0;
+
+}
+
+uchar i2c_reg_read (uchar chip, uchar reg)
+{
+ PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg));
+ return 0;
+}
+
+void i2c_reg_write(uchar chip, uchar reg, uchar val)
+{
+ PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val));
+}
+
+#endif /* CONFIG_HARD_I2C */
diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c
new file mode 100644
index 000000000..af7d63414
--- /dev/null
+++ b/cpu/pxa/interrupts.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+extern void reset_cpu (ulong addr);
+
+#ifdef CONFIG_USE_IRQ
+/* enable IRQ/FIQ interrupts */
+void enable_interrupts (void)
+{
+#error: interrupts not implemented yet
+}
+
+
+/*
+ * disable IRQ/FIQ interrupts
+ * returns true if interrupts had been enabled before we disabled them
+ */
+int disable_interrupts (void)
+{
+#error: interrupts not implemented yet
+}
+#else
+void enable_interrupts (void)
+{
+ return;
+}
+int disable_interrupts (void)
+{
+ return 0;
+}
+#endif
+
+
+
+void bad_mode (void)
+{
+ panic ("Resetting CPU ...\n");
+ reset_cpu (0);
+}
+
+void show_regs (struct pt_regs *regs)
+{
+ unsigned long flags;
+ const char *processor_modes[] = {
+ "USER_26", "FIQ_26", "IRQ_26", "SVC_26",
+ "UK4_26", "UK5_26", "UK6_26", "UK7_26",
+ "UK8_26", "UK9_26", "UK10_26", "UK11_26",
+ "UK12_26", "UK13_26", "UK14_26", "UK15_26",
+ "USER_32", "FIQ_32", "IRQ_32", "SVC_32",
+ "UK4_32", "UK5_32", "UK6_32", "ABT_32",
+ "UK8_32", "UK9_32", "UK10_32", "UND_32",
+ "UK12_32", "UK13_32", "UK14_32", "SYS_32"
+ };
+
+ flags = condition_codes (regs);
+
+ printf ("pc : [<%08lx>] lr : [<%08lx>]\n"
+ "sp : %08lx ip : %08lx fp : %08lx\n",
+ instruction_pointer (regs),
+ regs->ARM_lr, regs->ARM_sp, regs->ARM_ip, regs->ARM_fp);
+ printf ("r10: %08lx r9 : %08lx r8 : %08lx\n",
+ regs->ARM_r10, regs->ARM_r9, regs->ARM_r8);
+ printf ("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n",
+ regs->ARM_r7, regs->ARM_r6, regs->ARM_r5, regs->ARM_r4);
+ printf ("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n",
+ regs->ARM_r3, regs->ARM_r2, regs->ARM_r1, regs->ARM_r0);
+ printf ("Flags: %c%c%c%c",
+ flags & CC_N_BIT ? 'N' : 'n',
+ flags & CC_Z_BIT ? 'Z' : 'z',
+ flags & CC_C_BIT ? 'C' : 'c', flags & CC_V_BIT ? 'V' : 'v');
+ printf (" IRQs %s FIQs %s Mode %s%s\n",
+ interrupts_enabled (regs) ? "on" : "off",
+ fast_interrupts_enabled (regs) ? "on" : "off",
+ processor_modes[processor_mode (regs)],
+ thumb_mode (regs) ? " (T)" : "");
+}
+
+void do_undefined_instruction (struct pt_regs *pt_regs)
+{
+ printf ("undefined instruction\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_software_interrupt (struct pt_regs *pt_regs)
+{
+ printf ("software interrupt\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_prefetch_abort (struct pt_regs *pt_regs)
+{
+ printf ("prefetch abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_data_abort (struct pt_regs *pt_regs)
+{
+ printf ("data abort\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_not_used (struct pt_regs *pt_regs)
+{
+ printf ("not used\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_fiq (struct pt_regs *pt_regs)
+{
+ printf ("fast interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+void do_irq (struct pt_regs *pt_regs)
+{
+ printf ("interrupt request\n");
+ show_regs (pt_regs);
+ bad_mode ();
+}
+
+
+int interrupt_init (void)
+{
+ /* nothing happens here - we don't setup any IRQs */
+ return (0);
+}
+
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ return get_timer_masked ();
+}
+
+void set_timer (ulong t)
+{
+ /* nop */
+}
+
+void udelay (unsigned long usec)
+{
+ udelay_masked (usec);
+}
+
+
+void reset_timer_masked (void)
+{
+ OSCR = 0;
+}
+
+ulong get_timer_masked (void)
+{
+ return OSCR;
+}
+
+void udelay_masked (unsigned long usec)
+{
+ ulong tmo;
+
+ tmo = usec / 1000;
+ tmo *= CFG_HZ;
+ tmo /= 1000;
+
+ reset_timer_masked ();
+
+ while (tmo >= get_timer_masked ())
+ /*NOP*/;
+}
diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
new file mode 100644
index 000000000..c9d5f70bc
--- /dev/null
+++ b/cpu/pxa/serial.c
@@ -0,0 +1,166 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+
+void serial_setbrg (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ unsigned int quot = 0;
+
+ if (gd->baudrate == 1200)
+ quot = 192;
+ else if (gd->baudrate == 9600)
+ quot = 96;
+ else if (gd->baudrate == 19200)
+ quot = 48;
+ else if (gd->baudrate == 38400)
+ quot = 24;
+ else if (gd->baudrate == 57600)
+ quot = 16;
+ else if (gd->baudrate == 115200)
+ quot = 8;
+ else
+ hang ();
+
+#ifdef CONFIG_FFUART
+
+ CKEN |= CKEN6_FFUART;
+
+ FFIER = 0; /* Disable for now */
+ FFFCR = 0; /* No fifos enabled */
+
+ /* set baud rate */
+ FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
+ FFDLL = quot & 0xff;
+ FFDLH = quot >> 8;
+ FFLCR = LCR_WLS0 | LCR_WLS1;
+
+ FFIER = IER_UUE; /* Enable FFUART */
+
+#elif defined(CONFIG_BTUART)
+ CKEN |= CKEN7_BTUART;
+
+ BTIER = 0;
+ BTFCR = 0;
+
+ /* set baud rate */
+ BTLCR = LCR_DLAB;
+ BTDLL = quot & 0xff;
+ BTDLH = quot >> 8;
+ BTLCR = LCR_WLS0 | LCR_WLS1;
+
+ BTIER = IER_UUE; /* Enable BFUART */
+
+#elif defined(CONFIG_STUART)
+#error "Bad: not implemented yet!"
+#else
+#error "Bad: you didn't configured serial ..."
+#endif
+}
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init (void)
+{
+ serial_setbrg ();
+
+ return (0);
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc (const char c)
+{
+#ifdef CONFIG_FFUART
+ /* wait for room in the tx FIFO on FFUART */
+ while ((FFLSR & LSR_TEMT) == 0);
+
+ FFTHR = c;
+#elif defined(CONFIG_BTUART)
+ while ((BTLSR & LSR_TEMT ) == 0 );
+ BTTHR = c;
+#elif defined(CONFIG_STUART)
+#endif
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc ('\r');
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_tstc (void)
+{
+#ifdef CONFIG_FFUART
+ return FFLSR & LSR_DR;
+#elif defined(CONFIG_BTUART)
+ return BTLSR & LSR_DR;
+#elif defined(CONFIG_STUART)
+#endif
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc (void)
+{
+#ifdef CONFIG_FFUART
+ while (!(FFLSR & LSR_DR));
+
+ return (char) FFRBR & 0xff;
+#elif defined(CONFIG_BTUART)
+ while (!(BTLSR & LSR_DR));
+
+ return (char) BTRBR & 0xff;
+#elif defined(CONFIG_STUART)
+#endif
+}
+
+void
+serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S
new file mode 100644
index 000000000..95b30e44e
--- /dev/null
+++ b/cpu/pxa/start.S
@@ -0,0 +1,474 @@
+/*
+ * armboot - Startup Code for XScale
+ *
+ * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
+ * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
+ * Copyright (C) 2000 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2001 Alex Züpke <azu@sysgo.de>
+ * Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
+ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ * Copyright (C) 2003 Kai-Uwe Bloehm <kai-uwe.bloem@auerswald.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+.globl _start
+_start: b reset
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction: .word undefined_instruction
+_software_interrupt: .word software_interrupt
+_prefetch_abort: .word prefetch_abort
+_data_abort: .word data_abort
+_not_used: .word not_used
+_irq: .word irq
+_fiq: .word fiq
+
+ .balignl 16,0xdeadbeef
+
+
+/*
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * - relocate armboot to ram
+ * - setup stack
+ * - jump to second stage
+ */
+
+/*
+ * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
+ */
+_TEXT_BASE:
+ .word TEXT_BASE
+
+.globl _armboot_start
+_armboot_start:
+ .word _start
+
+/*
+ * Note: _armboot_end_data and _armboot_end are defined
+ * by the (board-dependent) linker script.
+ * _armboot_end_data is the first usable FLASH address after armboot
+ */
+.globl _armboot_end_data
+_armboot_end_data:
+ .word armboot_end_data
+.globl _armboot_end
+_armboot_end:
+ .word armboot_end
+
+/*
+ * This is defined in the board specific linker script
+ */
+.globl _bss_start
+_bss_start:
+ .word bss_start
+
+.globl _bss_end
+_bss_end:
+ .word bss_end
+
+/*
+ * _armboot_real_end is the first usable RAM address behind armboot
+ * and the various stacks
+ */
+.globl _armboot_real_end
+_armboot_real_end:
+ .word 0x0badc0de
+
+/*
+ * We relocate uboot to this address (end of RAM - 128 KiB)
+ */
+.globl _uboot_reloc
+_uboot_reloc:
+ .word TEXT_BASE
+
+#ifdef CONFIG_USE_IRQ
+/* IRQ stack memory (calculated at run-time) */
+.globl IRQ_STACK_START
+IRQ_STACK_START:
+ .word 0x0badc0de
+
+/* IRQ stack memory (calculated at run-time) */
+.globl FIQ_STACK_START
+FIQ_STACK_START:
+ .word 0x0badc0de
+#endif
+
+
+/****************************************************************************/
+/* */
+/* the actual reset code */
+/* */
+/****************************************************************************/
+
+reset:
+ mrs r0,cpsr /* set the cpu to SVC32 mode */
+ bic r0,r0,#0x1f /* (superviser mode, M=10011) */
+ orr r0,r0,#0x13
+ msr cpsr,r0
+
+ bl cpu_init_crit /* we do sys-critical inits */
+
+relocate: /* relocate U-Boot to RAM */
+ adr r0, _start /* r0 <- current position of code */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
+
+ ldr r2, _armboot_start
+ ldr r3, _armboot_end
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+
+ /* Set up the stack */
+
+stack_setup:
+
+ ldr r0, _uboot_reloc /* upper 128 KiB: relocated uboot */
+ sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
+ /* FIXME: bdinfo should be here */
+ sub sp, r0, #12 /* leave 3 words for abort-stack */
+
+clear_bss:
+
+ ldr r0, _bss_start /* find start of bss segment */
+ add r0, r0, #4 /* start at first byte of bss */
+ ldr r1, _bss_end /* stop here */
+ mov r2, #0x00000000 /* clear */
+
+clbss_l:str r2, [r0] /* clear loop... */
+ add r0, r0, #4
+ cmp r0, r1
+ bne clbss_l
+
+
+ ldr pc, _start_armboot
+
+_start_armboot: .word start_armboot
+
+
+/****************************************************************************/
+/* */
+/* CPU_init_critical registers */
+/* */
+/* - setup important registers */
+/* - setup memory timing */
+/* */
+/****************************************************************************/
+
+/* Interrupt-Controller base address */
+IC_BASE: .word 0x40d00000
+#define ICMR 0x04
+
+/* Reset-Controller */
+RST_BASE: .word 0x40f00030
+#define RCSR 0x00
+
+/* Operating System Timer */
+OSTIMER_BASE: .word 0x40a00000
+#define OSMR3 0x0C
+#define OSCR 0x10
+#define OWER 0x18
+#define OIER 0x1C
+
+/* Clock Manager Registers */
+CC_BASE: .word 0x41300000
+#define CCCR 0x00
+cpuspeed: .word CFG_CPUSPEED
+
+
+ /* RS: ??? */
+ .macro CPWAIT
+ mrc p15,0,r0,c2,c0,0
+ mov r0,r0
+ sub pc,pc,#4
+ .endm
+
+
+cpu_init_crit:
+
+ /* mask all IRQs */
+ ldr r0, IC_BASE
+ mov r1, #0x00
+ str r1, [r0, #ICMR]
+
+#if defined(CFG_CPUSPEED)
+
+ /* set clock speed */
+ ldr r0, CC_BASE
+ ldr r1, cpuspeed
+ str r1, [r0, #CCCR]
+ mov r0, #2
+ mcr p14, 0, r0, c6, c0, 0
+
+setspeed_done:
+#endif
+
+ /*
+ * before relocating, we have to setup RAM timing
+ * because memory timing is board-dependend, you will
+ * find a memsetup.S in your board directory.
+ */
+ mov ip, lr
+ bl memsetup
+ mov lr, ip
+
+ /* Memory interfaces are working. Disable MMU and enable I-cache. */
+
+ ldr r0, =0x2001 /* enable access to all coproc. */
+ mcr p15, 0, r0, c15, c1, 0
+ CPWAIT
+
+ mcr p15, 0, r0, c7, c10, 4 /* drain the write & fill buffers */
+ CPWAIT
+
+ mcr p15, 0, r0, c7, c7, 0 /* flush Icache, Dcache and BTB */
+ CPWAIT
+
+ mcr p15, 0, r0, c8, c7, 0 /* flush instuction and data TLBs */
+ CPWAIT
+
+ /* Enable the Icache */
+/*
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #0x1800
+ mcr p15, 0, r0, c1, c0, 0
+ CPWAIT
+*/
+ mov pc, lr
+
+
+/****************************************************************************/
+/* */
+/* Interrupt handling */
+/* */
+/****************************************************************************/
+
+/* IRQ stack frame */
+
+#define S_FRAME_SIZE 72
+
+#define S_OLD_R0 68
+#define S_PSR 64
+#define S_PC 60
+#define S_LR 56
+#define S_SP 52
+
+#define S_IP 48
+#define S_FP 44
+#define S_R10 40
+#define S_R9 36
+#define S_R8 32
+#define S_R7 28
+#define S_R6 24
+#define S_R5 20
+#define S_R4 16
+#define S_R3 12
+#define S_R2 8
+#define S_R1 4
+#define S_R0 0
+
+#define MODE_SVC 0x13
+
+ /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
+
+ .macro bad_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} /* Calling r0-r12 */
+ add r8, sp, #S_PC
+
+ ldr r2, _armboot_end
+ add r2, r2, #CONFIG_STACKSIZE
+ sub r2, r2, #8
+ ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
+ add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
+
+ add r5, sp, #S_SP
+ mov r1, lr
+ stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
+ mov r0, sp
+ .endm
+
+
+ /* use irq_save_user_regs / irq_restore_user_regs for */
+ /* IRQ/FIQ handling */
+
+ .macro irq_save_user_regs
+ sub sp, sp, #S_FRAME_SIZE
+ stmia sp, {r0 - r12} /* Calling r0-r12 */
+ add r8, sp, #S_PC
+ stmdb r8, {sp, lr}^ /* Calling SP, LR */
+ str lr, [r8, #0] /* Save calling PC */
+ mrs r6, spsr
+ str r6, [r8, #4] /* Save CPSR */
+ str r0, [r8, #8] /* Save OLD_R0 */
+ mov r0, sp
+ .endm
+
+ .macro irq_restore_user_regs
+ ldmia sp, {r0 - lr}^ @ Calling r0 - lr
+ mov r0, r0
+ ldr lr, [sp, #S_PC] @ Get PC
+ add sp, sp, #S_FRAME_SIZE
+ subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ .endm
+
+ .macro get_bad_stack
+ ldr r13, _armboot_end @ setup our mode stack
+ add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
+ sub r13, r13, #8
+
+ str lr, [r13] @ save caller lr / spsr
+ mrs lr, spsr
+ str lr, [r13, #4]
+
+ mov r13, #MODE_SVC @ prepare SVC-Mode
+ msr spsr_c, r13
+ mov lr, pc
+ movs pc, lr
+ .endm
+
+ .macro get_irq_stack @ setup IRQ stack
+ ldr sp, IRQ_STACK_START
+ .endm
+
+ .macro get_fiq_stack @ setup FIQ stack
+ ldr sp, FIQ_STACK_START
+ .endm
+
+
+/****************************************************************************/
+/* */
+/* exception handlers */
+/* */
+/****************************************************************************/
+
+ .align 5
+undefined_instruction:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_undefined_instruction
+
+ .align 5
+software_interrupt:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_software_interrupt
+
+ .align 5
+prefetch_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_prefetch_abort
+
+ .align 5
+data_abort:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_data_abort
+
+ .align 5
+not_used:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_not_used
+
+#ifdef CONFIG_USE_IRQ
+
+ .align 5
+irq:
+ get_irq_stack
+ irq_save_user_regs
+ bl do_irq
+ irq_restore_user_regs
+
+ .align 5
+fiq:
+ get_fiq_stack
+ irq_save_user_regs /* someone ought to write a more */
+ bl do_fiq /* effiction fiq_save_user_regs */
+ irq_restore_user_regs
+
+#else
+
+ .align 5
+irq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_irq
+
+ .align 5
+fiq:
+ get_bad_stack
+ bad_save_user_regs
+ bl do_fiq
+
+#endif
+
+/****************************************************************************/
+/* */
+/* Reset function: the PXA250 doesn't have a reset function, so we have to */
+/* perform a watchdog timeout for a soft reset. */
+/* */
+/****************************************************************************/
+
+ .align 5
+.globl reset_cpu
+
+ /* FIXME: this code is PXA250 specific. How is this handled on */
+ /* other XScale processors? */
+
+reset_cpu:
+
+ /* We set OWE:WME (watchdog enable) and wait until timeout happens */
+
+ ldr r0, OSTIMER_BASE
+ ldr r1, [r0, #OWER]
+ orr r1, r1, #0x0001 /* bit0: WME */
+ str r1, [r0, #OWER]
+
+ /* OS timer does only wrap every 1165 seconds, so we have to set */
+ /* the match register as well. */
+
+ ldr r1, [r0, #OSCR] /* read OS timer */
+ add r1, r1, #0x800 /* let OSMR3 match after */
+ add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
+ str r1, [r0, #OSMR3]
+
+reset_endless:
+
+ b reset_endless
+
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