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-rw-r--r--drivers/qe/uec.c159
-rw-r--r--drivers/qe/uec.h1
-rw-r--r--drivers/qe/uec_phy.c103
-rw-r--r--drivers/qe/uec_phy.h8
4 files changed, 239 insertions, 32 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 344c64999..bba3ef2c6 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -34,12 +34,12 @@
#ifdef CONFIG_UEC_ETH1
static uec_info_t eth1_uec_info = {
.uf_info = {
- .ucc_num = CFG_UEC1_UCC_NUM,
- .rx_clock = CFG_UEC1_RX_CLK,
- .tx_clock = CFG_UEC1_TX_CLK,
- .eth_type = CFG_UEC1_ETH_TYPE,
+ .ucc_num = CONFIG_SYS_UEC1_UCC_NUM,
+ .rx_clock = CONFIG_SYS_UEC1_RX_CLK,
+ .tx_clock = CONFIG_SYS_UEC1_TX_CLK,
+ .eth_type = CONFIG_SYS_UEC1_ETH_TYPE,
},
-#if (CFG_UEC1_ETH_TYPE == FAST_ETH)
+#if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
.num_threads_tx = UEC_NUM_OF_THREADS_1,
.num_threads_rx = UEC_NUM_OF_THREADS_1,
#else
@@ -50,19 +50,19 @@ static uec_info_t eth1_uec_info = {
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
- .phy_address = CFG_UEC1_PHY_ADDR,
- .enet_interface = CFG_UEC1_INTERFACE_MODE,
+ .phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
+ .enet_interface = CONFIG_SYS_UEC1_INTERFACE_MODE,
};
#endif
#ifdef CONFIG_UEC_ETH2
static uec_info_t eth2_uec_info = {
.uf_info = {
- .ucc_num = CFG_UEC2_UCC_NUM,
- .rx_clock = CFG_UEC2_RX_CLK,
- .tx_clock = CFG_UEC2_TX_CLK,
- .eth_type = CFG_UEC2_ETH_TYPE,
+ .ucc_num = CONFIG_SYS_UEC2_UCC_NUM,
+ .rx_clock = CONFIG_SYS_UEC2_RX_CLK,
+ .tx_clock = CONFIG_SYS_UEC2_TX_CLK,
+ .eth_type = CONFIG_SYS_UEC2_ETH_TYPE,
},
-#if (CFG_UEC2_ETH_TYPE == FAST_ETH)
+#if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
.num_threads_tx = UEC_NUM_OF_THREADS_1,
.num_threads_rx = UEC_NUM_OF_THREADS_1,
#else
@@ -73,19 +73,19 @@ static uec_info_t eth2_uec_info = {
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
- .phy_address = CFG_UEC2_PHY_ADDR,
- .enet_interface = CFG_UEC2_INTERFACE_MODE,
+ .phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
+ .enet_interface = CONFIG_SYS_UEC2_INTERFACE_MODE,
};
#endif
#ifdef CONFIG_UEC_ETH3
static uec_info_t eth3_uec_info = {
.uf_info = {
- .ucc_num = CFG_UEC3_UCC_NUM,
- .rx_clock = CFG_UEC3_RX_CLK,
- .tx_clock = CFG_UEC3_TX_CLK,
- .eth_type = CFG_UEC3_ETH_TYPE,
+ .ucc_num = CONFIG_SYS_UEC3_UCC_NUM,
+ .rx_clock = CONFIG_SYS_UEC3_RX_CLK,
+ .tx_clock = CONFIG_SYS_UEC3_TX_CLK,
+ .eth_type = CONFIG_SYS_UEC3_ETH_TYPE,
},
-#if (CFG_UEC3_ETH_TYPE == FAST_ETH)
+#if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
.num_threads_tx = UEC_NUM_OF_THREADS_1,
.num_threads_rx = UEC_NUM_OF_THREADS_1,
#else
@@ -96,19 +96,19 @@ static uec_info_t eth3_uec_info = {
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
- .phy_address = CFG_UEC3_PHY_ADDR,
- .enet_interface = CFG_UEC3_INTERFACE_MODE,
+ .phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
+ .enet_interface = CONFIG_SYS_UEC3_INTERFACE_MODE,
};
#endif
#ifdef CONFIG_UEC_ETH4
static uec_info_t eth4_uec_info = {
.uf_info = {
- .ucc_num = CFG_UEC4_UCC_NUM,
- .rx_clock = CFG_UEC4_RX_CLK,
- .tx_clock = CFG_UEC4_TX_CLK,
- .eth_type = CFG_UEC4_ETH_TYPE,
+ .ucc_num = CONFIG_SYS_UEC4_UCC_NUM,
+ .rx_clock = CONFIG_SYS_UEC4_RX_CLK,
+ .tx_clock = CONFIG_SYS_UEC4_TX_CLK,
+ .eth_type = CONFIG_SYS_UEC4_ETH_TYPE,
},
-#if (CFG_UEC4_ETH_TYPE == FAST_ETH)
+#if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
.num_threads_tx = UEC_NUM_OF_THREADS_1,
.num_threads_rx = UEC_NUM_OF_THREADS_1,
#else
@@ -119,12 +119,58 @@ static uec_info_t eth4_uec_info = {
.riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
.tx_bd_ring_len = 16,
.rx_bd_ring_len = 16,
- .phy_address = CFG_UEC4_PHY_ADDR,
- .enet_interface = CFG_UEC4_INTERFACE_MODE,
+ .phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
+ .enet_interface = CONFIG_SYS_UEC4_INTERFACE_MODE,
+};
+#endif
+#ifdef CONFIG_UEC_ETH5
+static uec_info_t eth5_uec_info = {
+ .uf_info = {
+ .ucc_num = CONFIG_SYS_UEC5_UCC_NUM,
+ .rx_clock = CONFIG_SYS_UEC5_RX_CLK,
+ .tx_clock = CONFIG_SYS_UEC5_TX_CLK,
+ .eth_type = CONFIG_SYS_UEC5_ETH_TYPE,
+ },
+#if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .tx_bd_ring_len = 16,
+ .rx_bd_ring_len = 16,
+ .phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
+ .enet_interface = CONFIG_SYS_UEC5_INTERFACE_MODE,
+};
+#endif
+#ifdef CONFIG_UEC_ETH6
+static uec_info_t eth6_uec_info = {
+ .uf_info = {
+ .ucc_num = CONFIG_SYS_UEC6_UCC_NUM,
+ .rx_clock = CONFIG_SYS_UEC6_RX_CLK,
+ .tx_clock = CONFIG_SYS_UEC6_TX_CLK,
+ .eth_type = CONFIG_SYS_UEC6_ETH_TYPE,
+ },
+#if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
+ .num_threads_tx = UEC_NUM_OF_THREADS_1,
+ .num_threads_rx = UEC_NUM_OF_THREADS_1,
+#else
+ .num_threads_tx = UEC_NUM_OF_THREADS_4,
+ .num_threads_rx = UEC_NUM_OF_THREADS_4,
+#endif
+ .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+ .tx_bd_ring_len = 16,
+ .rx_bd_ring_len = 16,
+ .phy_address = CONFIG_SYS_UEC6_PHY_ADDR,
+ .enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE,
};
#endif
-#define MAXCONTROLLERS (4)
+#define MAXCONTROLLERS (6)
static struct eth_device *devlist[MAXCONTROLLERS];
@@ -424,6 +470,7 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
upsmr |= (UPSMR_RPM | UPSMR_TBIM);
break;
case ENET_1000_RGMII_RXID:
+ case ENET_1000_RGMII_ID:
case ENET_1000_RGMII:
maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
upsmr |= UPSMR_RPM;
@@ -639,6 +686,31 @@ static void phy_change(struct eth_device *dev)
&& !defined(BITBANGMII)
/*
+ * Find a device index from the devlist by name
+ *
+ * Returns:
+ * The index where the device is located, -1 on error
+ */
+static int uec_miiphy_find_dev_by_name(char *devname)
+{
+ int i;
+
+ for (i = 0; i < MAXCONTROLLERS; i++) {
+ if (strncmp(devname, devlist[i]->name, strlen(devname)) == 0) {
+ break;
+ }
+ }
+
+ /* If device cannot be found, returns -1 */
+ if (i == MAXCONTROLLERS) {
+ debug ("%s: device %s not found in devlist\n", __FUNCTION__, devname);
+ i = -1;
+ }
+
+ return i;
+}
+
+/*
* Read a MII PHY register.
*
* Returns:
@@ -647,8 +719,16 @@ static void phy_change(struct eth_device *dev)
static int uec_miiphy_read(char *devname, unsigned char addr,
unsigned char reg, unsigned short *value)
{
- *value = uec_read_phy_reg(devlist[0], addr, reg);
+ int devindex = 0;
+ if (devname == NULL || value == NULL) {
+ debug("%s: NULL pointer given\n", __FUNCTION__);
+ } else {
+ devindex = uec_miiphy_find_dev_by_name(devname);
+ if (devindex >= 0) {
+ *value = uec_read_phy_reg(devlist[devindex], addr, reg);
+ }
+ }
return 0;
}
@@ -661,11 +741,18 @@ static int uec_miiphy_read(char *devname, unsigned char addr,
static int uec_miiphy_write(char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
- uec_write_phy_reg(devlist[0], addr, reg, value);
+ int devindex = 0;
+ if (devname == NULL) {
+ debug("%s: NULL pointer given\n", __FUNCTION__);
+ } else {
+ devindex = uec_miiphy_find_dev_by_name(devname);
+ if (devindex >= 0) {
+ uec_write_phy_reg(devlist[devindex], addr, reg, value);
+ }
+ }
return 0;
}
-
#endif
static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
@@ -1368,6 +1455,14 @@ int uec_initialize(int index)
#ifdef CONFIG_UEC_ETH4
uec_info = &eth4_uec_info;
#endif
+ } else if (index == 4) {
+#ifdef CONFIG_UEC_ETH5
+ uec_info = &eth5_uec_info;
+#endif
+ } else if (index == 5) {
+#ifdef CONFIG_UEC_ETH6
+ uec_info = &eth6_uec_info;
+#endif
} else {
printf("%s: index is illegal.\n", __FUNCTION__);
return -EINVAL;
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index e357a92bb..0b644996b 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -642,6 +642,7 @@ typedef enum enet_interface {
ENET_100_RGMII,
ENET_1000_GMII,
ENET_1000_RGMII,
+ ENET_1000_RGMII_ID,
ENET_1000_RGMII_RXID,
ENET_1000_TBI,
ENET_1000_RTBI
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 186922e0c..829f08285 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -44,6 +44,54 @@
#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
#endif /* UEC_VERBOSE_DEBUG */
+/*--------------------------------------------------------------------+
+ * Fixed PHY (PHY-less) support for Ethernet Ports.
+ *
+ * Copied from cpu/ppc4xx/4xx_enet.c
+ *--------------------------------------------------------------------*/
+
+/*
+ * Some boards do not have a PHY for each ethernet port. These ports
+ * are known as Fixed PHY (or PHY-less) ports. For such ports, set
+ * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
+ * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
+ * duplex should be for these ports in the board configuration
+ * file.
+ *
+ * For Example:
+ * #define CONFIG_FIXED_PHY 0xFFFFFFFF
+ *
+ * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
+ * #define CONFIG_PHY1_ADDR 1
+ * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
+ * #define CONFIG_PHY3_ADDR 3
+ *
+ * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
+ * {devnum, speed, duplex},
+ *
+ * #define CONFIG_SYS_FIXED_PHY_PORTS \
+ * CONFIG_SYS_FIXED_PHY_PORT(0,SPEED_100,DUPLEX_FULL) \
+ * CONFIG_SYS_FIXED_PHY_PORT(2,SPEED_100,DUPLEX_HALF)
+ */
+
+#ifndef CONFIG_FIXED_PHY
+#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
+#endif
+
+#ifndef CONFIG_SYS_FIXED_PHY_PORTS
+#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
+#endif
+
+struct fixed_phy_port {
+ unsigned int devnum; /* ethernet port */
+ unsigned int speed; /* specified speed 10,100 or 1000 */
+ unsigned int duplex; /* specified duplex FULL or HALF */
+};
+
+static const struct fixed_phy_port fixed_phy_port[] = {
+ CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
+};
+
static void config_genmii_advert (struct uec_mii_info *mii_info);
static void genmii_setup_forced (struct uec_mii_info *mii_info);
static void genmii_restart_aneg (struct uec_mii_info *mii_info);
@@ -376,6 +424,29 @@ static int bcm_init(struct uec_mii_info *mii_info)
return 0;
}
+static int marvell_init(struct uec_mii_info *mii_info)
+{
+ struct eth_device *edev = mii_info->dev;
+ uec_private_t *uec = edev->priv;
+
+ if (uec->uec_info->enet_interface == ENET_1000_RGMII_ID) {
+ int temp;
+
+ temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
+ temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
+ phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
+
+ temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
+ temp &= ~MII_M1111_HWCFG_MODE_MASK;
+ temp |= MII_M1111_HWCFG_MODE_RGMII;
+ phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
+
+ phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
+ }
+
+ return 0;
+}
+
static int marvell_read_status (struct uec_mii_info *mii_info)
{
u16 status;
@@ -510,6 +581,28 @@ static void dm9161_close (struct uec_mii_info *mii_info)
{
}
+static int fixed_phy_aneg (struct uec_mii_info *mii_info)
+{
+ mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
+ return 0;
+}
+
+static int fixed_phy_read_status (struct uec_mii_info *mii_info)
+{
+ int i = 0;
+
+ for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
+ if (mii_info->mii_id == fixed_phy_port[i].devnum) {
+ mii_info->speed = fixed_phy_port[i].speed;
+ mii_info->duplex = fixed_phy_port[i].duplex;
+ mii_info->link = 1; /* Link is always UP */
+ mii_info->pause = 0;
+ break;
+ }
+ }
+ return 0;
+}
+
static struct phy_info phy_info_dm9161 = {
.phy_id = 0x0181b880,
.phy_id_mask = 0x0ffffff0,
@@ -538,6 +631,7 @@ static struct phy_info phy_info_marvell = {
.phy_id_mask = 0xffffff00,
.name = "Marvell 88E11x1",
.features = MII_GBIT_FEATURES,
+ .init = &marvell_init,
.config_aneg = &marvell_config_aneg,
.read_status = &marvell_read_status,
.ack_interrupt = &marvell_ack_interrupt,
@@ -553,6 +647,14 @@ static struct phy_info phy_info_bcm5481 = {
.init = bcm_init,
};
+static struct phy_info phy_info_fixedphy = {
+ .phy_id = CONFIG_FIXED_PHY,
+ .phy_id_mask = CONFIG_FIXED_PHY,
+ .name = "Fixed PHY",
+ .config_aneg = fixed_phy_aneg,
+ .read_status = fixed_phy_read_status,
+};
+
static struct phy_info phy_info_genmii = {
.phy_id = 0x00000000,
.phy_id_mask = 0x00000000,
@@ -567,6 +669,7 @@ static struct phy_info *phy_info[] = {
&phy_info_dm9161a,
&phy_info_marvell,
&phy_info_bcm5481,
+ &phy_info_fixedphy,
&phy_info_genmii,
NULL
};
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index 6f769fb50..7ac1ff932 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -77,6 +77,14 @@
#define MII_M1011_IMASK_INIT 0x6400
#define MII_M1011_IMASK_CLEAR 0x0000
+/* 88E1111 PHY Register */
+#define MII_M1111_PHY_EXT_CR 0x14
+#define MII_M1111_RX_DELAY 0x80
+#define MII_M1111_TX_DELAY 0x2
+#define MII_M1111_PHY_EXT_SR 0x1b
+#define MII_M1111_HWCFG_MODE_MASK 0xf
+#define MII_M1111_HWCFG_MODE_RGMII 0xb
+
#define MII_DM9161_SCR 0x10
#define MII_DM9161_SCR_INIT 0x0610
#define MII_DM9161_SCR_RMII_INIT 0x0710
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-15 20:02:18 +0000