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-rw-r--r--include/asm-ppc/4xx_pcie.h14
-rw-r--r--include/asm-ppc/cache.h13
-rw-r--r--include/asm-ppc/cpm_8260.h8
-rw-r--r--include/asm-ppc/fsl_ddr_dimm_params.h84
-rw-r--r--include/asm-ppc/fsl_ddr_sdram.h12
-rw-r--r--include/asm-ppc/fsl_lbc.h138
-rw-r--r--include/asm-ppc/fsl_serdes.h10
-rw-r--r--include/asm-ppc/global_data.h11
-rw-r--r--include/asm-ppc/immap_83xx.h57
-rw-r--r--include/asm-ppc/immap_85xx.h80
-rw-r--r--include/asm-ppc/immap_86xx.h8
-rw-r--r--include/asm-ppc/io.h5
-rw-r--r--include/asm-ppc/iopin_8260.h40
-rw-r--r--include/asm-ppc/iopin_85xx.h40
-rw-r--r--include/asm-ppc/iopin_8xx.h128
-rw-r--r--include/asm-ppc/ppc4xx-ebc.h31
-rw-r--r--include/asm-ppc/ppc4xx-isram.h75
-rw-r--r--include/asm-ppc/ppc4xx-sdram.h22
-rw-r--r--include/asm-ppc/status_led.h6
-rw-r--r--include/asm-ppc/u-boot.h6
20 files changed, 566 insertions, 222 deletions
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h
index a7cf1e8f5..a0e88de11 100644
--- a/include/asm-ppc/4xx_pcie.h
+++ b/include/asm-ppc/4xx_pcie.h
@@ -18,9 +18,9 @@
#define DCRN_SDR0_CFGDATA 0x00f
#if defined(CONFIG_440SPE)
-#define CFG_PCIE_NR_PORTS 3
+#define CONFIG_SYS_PCIE_NR_PORTS 3
-#define CFG_PCIE_ADDR_HIGH 0x0000000d
+#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
@@ -32,9 +32,9 @@
#endif
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
-#define CFG_PCIE_NR_PORTS 2
+#define CONFIG_SYS_PCIE_NR_PORTS 2
-#define CFG_PCIE_ADDR_HIGH 0x0000000d
+#define CONFIG_SYS_PCIE_ADDR_HIGH 0x0000000d
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
@@ -44,9 +44,9 @@
#endif
#if defined(CONFIG_405EX)
-#define CFG_PCIE_NR_PORTS 2
+#define CONFIG_SYS_PCIE_NR_PORTS 2
-#define CFG_PCIE_ADDR_HIGH 0x00000000
+#define CONFIG_SYS_PCIE_ADDR_HIGH 0x00000000
#define DCRN_PCIE0_BASE 0x040
#define DCRN_PCIE1_BASE 0x060
@@ -406,7 +406,7 @@ static inline u32 sdr_base(int port)
return PCIE0_SDR;
case 1:
return PCIE1_SDR;
-#if CFG_PCIE_NR_PORTS > 2
+#if CONFIG_SYS_PCIE_NR_PORTS > 2
case 2:
return PCIE2_SDR;
#endif
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
index 9d9b9717d..53e8d05f5 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-ppc/cache.h
@@ -12,6 +12,8 @@
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
+#elif defined(CONFIG_E500MC)
+#define L1_CACHE_SHIFT 6
#else
#define L1_CACHE_SHIFT 5
#endif
@@ -19,10 +21,10 @@
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
- * For compatibility reasons support the CFG_CACHELINE_SIZE too
+ * For compatibility reasons support the CONFIG_SYS_CACHELINE_SIZE too
*/
-#ifndef CFG_CACHELINE_SIZE
-#define CFG_CACHELINE_SIZE L1_CACHE_BYTES
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
#endif
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
@@ -44,9 +46,10 @@ extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache(void);
extern void invalidate_dcache(void);
-#ifdef CFG_INIT_RAM_LOCK
+extern void invalidate_icache(void);
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
-#endif /* CFG_INIT_RAM_LOCK */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK */
#endif /* __ASSEMBLY__ */
/* prep registers for L2 */
diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h
index 2a9774ade..7e06940c9 100644
--- a/include/asm-ppc/cpm_8260.h
+++ b/include/asm-ppc/cpm_8260.h
@@ -141,16 +141,16 @@ typedef struct cpm_buf_desc {
/* Parameter RAM offsets from the base.
*/
-#ifndef CFG_CPM_POST_WORD_ADDR
+#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR
#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
#else
-#define CPM_POST_WORD_ADDR CFG_CPM_POST_WORD_ADDR
+#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR
#endif
-#ifndef CFG_CPM_BOOTCOUNT_ADDR
+#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR
#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong))
#else
-#define CPM_BOOTCOUNT_ADDR CFG_CPM_BOOTCOUNT_ADDR
+#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR
#endif
#define PROFF_SCC1 ((uint)0x8000)
diff --git a/include/asm-ppc/fsl_ddr_dimm_params.h b/include/asm-ppc/fsl_ddr_dimm_params.h
new file mode 100644
index 000000000..c794eedfe
--- /dev/null
+++ b/include/asm-ppc/fsl_ddr_dimm_params.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#ifndef DDR2_DIMM_PARAMS_H
+#define DDR2_DIMM_PARAMS_H
+
+/* Parameters for a DDR2 dimm computed from the SPD */
+typedef struct dimm_params_s {
+
+ /* DIMM organization parameters */
+ char mpart[19]; /* guaranteed null terminated */
+
+ unsigned int n_ranks;
+ unsigned long long rank_density;
+ unsigned long long capacity;
+ unsigned int data_width;
+ unsigned int primary_sdram_width;
+ unsigned int ec_sdram_width;
+ unsigned int registered_dimm;
+
+ /* SDRAM device parameters */
+ unsigned int n_row_addr;
+ unsigned int n_col_addr;
+ unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
+ unsigned int n_banks_per_sdram_device;
+ unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
+ unsigned int row_density;
+
+ /* used in computing base address of DIMMs */
+ unsigned long long base_address;
+
+ /* DIMM timing parameters */
+
+ /*
+ * SDRAM clock periods
+ * The range for these are 1000-10000 so a short should be sufficient
+ */
+ unsigned int tCKmin_X_ps;
+ unsigned int tCKmin_X_minus_1_ps;
+ unsigned int tCKmin_X_minus_2_ps;
+ unsigned int tCKmax_ps;
+
+ /* SPD-defined CAS latencies */
+ unsigned int caslat_X;
+ unsigned int caslat_X_minus_1;
+ unsigned int caslat_X_minus_2;
+
+ unsigned int caslat_lowest_derated; /* Derated CAS latency */
+
+ /* basic timing parameters */
+ unsigned int tRCD_ps;
+ unsigned int tRP_ps;
+ unsigned int tRAS_ps;
+
+ unsigned int tWR_ps; /* maximum = 63750 ps */
+ unsigned int tWTR_ps; /* maximum = 63750 ps */
+ unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns
+ = 511750 ps */
+
+ unsigned int tRRD_ps; /* maximum = 63750 ps */
+ unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
+
+ unsigned int refresh_rate_ps;
+
+ unsigned int tIS_ps; /* byte 32, spd->ca_setup */
+ unsigned int tIH_ps; /* byte 33, spd->ca_hold */
+ unsigned int tDS_ps; /* byte 34, spd->data_setup */
+ unsigned int tDH_ps; /* byte 35, spd->data_hold */
+ unsigned int tRTP_ps; /* byte 38, spd->trtp */
+ unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */
+ unsigned int tQHS_ps; /* byte 45, spd->tqhs */
+} dimm_params_t;
+
+extern unsigned int ddr_compute_dimm_parameters(
+ const generic_spd_eeprom_t *spd,
+ dimm_params_t *pdimm,
+ unsigned int dimm_number);
+
+#endif
diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h
index 8adde3424..c1ea7cd6b 100644
--- a/include/asm-ppc/fsl_ddr_sdram.h
+++ b/include/asm-ppc/fsl_ddr_sdram.h
@@ -36,6 +36,18 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t;
typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
#endif
+/* define bank(chip select) interleaving mode */
+#define FSL_DDR_CS0_CS1 0x40
+#define FSL_DDR_CS2_CS3 0x20
+#define FSL_DDR_CS0_CS1_AND_CS2_CS3 (FSL_DDR_CS0_CS1 | FSL_DDR_CS2_CS3)
+#define FSL_DDR_CS0_CS1_CS2_CS3 (FSL_DDR_CS0_CS1_AND_CS2_CS3 | 0x04)
+
+/* define memory controller interleaving mode */
+#define FSL_DDR_CACHE_LINE_INTERLEAVING 0x0
+#define FSL_DDR_PAGE_INTERLEAVING 0x1
+#define FSL_DDR_BANK_INTERLEAVING 0x2
+#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
+
/* Record of register values computed */
typedef struct fsl_ddr_cfg_regs_s {
struct {
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index ea49ddc51..51fc5c13b 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -69,6 +69,14 @@
#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
#endif
+/* Convert an address into the right format for the BR registers */
+#ifdef CONFIG_PHYS_64BIT
+#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
+ ((x & 0x300000000ULL) >> 19)))
+#else
+#define BR_PHYS_ADDR(x) (x & 0xffff8000)
+#endif
+
/* OR - Option Registers
*/
#define OR0 0x5004 /* Register offset to immr */
@@ -307,4 +315,134 @@
#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
+/* FMR - Flash Mode Register
+ */
+#define FMR_CWTO 0x0000F000
+#define FMR_CWTO_SHIFT 12
+#define FMR_BOOT 0x00000800
+#define FMR_ECCM 0x00000100
+#define FMR_AL 0x00000030
+#define FMR_AL_SHIFT 4
+#define FMR_OP 0x00000003
+#define FMR_OP_SHIFT 0
+
+/* FIR - Flash Instruction Register
+ */
+#define FIR_OP0 0xF0000000
+#define FIR_OP0_SHIFT 28
+#define FIR_OP1 0x0F000000
+#define FIR_OP1_SHIFT 24
+#define FIR_OP2 0x00F00000
+#define FIR_OP2_SHIFT 20
+#define FIR_OP3 0x000F0000
+#define FIR_OP3_SHIFT 16
+#define FIR_OP4 0x0000F000
+#define FIR_OP4_SHIFT 12
+#define FIR_OP5 0x00000F00
+#define FIR_OP5_SHIFT 8
+#define FIR_OP6 0x000000F0
+#define FIR_OP6_SHIFT 4
+#define FIR_OP7 0x0000000F
+#define FIR_OP7_SHIFT 0
+#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
+#define FIR_OP_CA 0x1 /* Issue current column address */
+#define FIR_OP_PA 0x2 /* Issue current block+page address */
+#define FIR_OP_UA 0x3 /* Issue user defined address */
+#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
+#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
+#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
+#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
+#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
+#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
+#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
+#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
+#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
+#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
+#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
+#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
+
+/* FCR - Flash Command Register
+ */
+#define FCR_CMD0 0xFF000000
+#define FCR_CMD0_SHIFT 24
+#define FCR_CMD1 0x00FF0000
+#define FCR_CMD1_SHIFT 16
+#define FCR_CMD2 0x0000FF00
+#define FCR_CMD2_SHIFT 8
+#define FCR_CMD3 0x000000FF
+#define FCR_CMD3_SHIFT 0
+/* FBAR - Flash Block Address Register
+ */
+#define FBAR_BLK 0x00FFFFFF
+
+/* FPAR - Flash Page Address Register
+ */
+#define FPAR_SP_PI 0x00007C00
+#define FPAR_SP_PI_SHIFT 10
+#define FPAR_SP_MS 0x00000200
+#define FPAR_SP_CI 0x000001FF
+#define FPAR_SP_CI_SHIFT 0
+#define FPAR_LP_PI 0x0003F000
+#define FPAR_LP_PI_SHIFT 12
+#define FPAR_LP_MS 0x00000800
+#define FPAR_LP_CI 0x000007FF
+#define FPAR_LP_CI_SHIFT 0
+
+/* LTESR - Transfer Error Status Register
+ */
+#define LTESR_BM 0x80000000
+#define LTESR_FCT 0x40000000
+#define LTESR_PAR 0x20000000
+#define LTESR_WP 0x04000000
+#define LTESR_ATMW 0x00800000
+#define LTESR_ATMR 0x00400000
+#define LTESR_CS 0x00080000
+#define LTESR_CC 0x00000001
+
+#ifndef __ASSEMBLY__
+/*
+ * Local Bus Controller Registers.
+ */
+typedef struct lbus_bank {
+ u32 br; /* Base Register */
+ u32 or; /* Option Register */
+} lbus_bank_t;
+
+typedef struct fsl_lbus {
+ lbus_bank_t bank[8];
+ u8 res0[0x28];
+ u32 mar; /* UPM Address Register */
+ u8 res1[0x4];
+ u32 mamr; /* UPMA Mode Register */
+ u32 mbmr; /* UPMB Mode Register */
+ u32 mcmr; /* UPMC Mode Register */
+ u8 res2[0x8];
+ u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
+ u32 mdr; /* UPM Data Register */
+ u8 res3[0x4];
+ u32 lsor; /* Special Operation Initiation Register */
+ u32 lsdmr; /* SDRAM Mode Register */
+ u8 res4[0x8];
+ u32 lurt; /* UPM Refresh Timer */
+ u32 lsrt; /* SDRAM Refresh Timer */
+ u8 res5[0x8];
+ u32 ltesr; /* Transfer Error Status Register */
+ u32 ltedr; /* Transfer Error Disable Register */
+ u32 lteir; /* Transfer Error Interrupt Register */
+ u32 lteatr; /* Transfer Error Attributes Register */
+ u32 ltear; /* Transfer Error Address Register */
+ u8 res6[0xC];
+ u32 lbcr; /* Configuration Register */
+ u32 lcrr; /* Clock Ratio Register */
+ u8 res7[0x8];
+ u32 fmr; /* Flash Mode Register */
+ u32 fir; /* Flash Instruction Register */
+ u32 fcr; /* Flash Command Register */
+ u32 fbar; /* Flash Block Addr Register */
+ u32 fpar; /* Flash Page Addr Register */
+ u32 fbcr; /* Flash Byte Count Register */
+ u8 res8[0xF08];
+} fsl_lbus_t;
+#endif /* __ASSEMBLY__ */
+
#endif /* __ASM_PPC_FSL_LBC_H */
diff --git a/include/asm-ppc/fsl_serdes.h b/include/asm-ppc/fsl_serdes.h
index 733f919cf..6da4b6ff9 100644
--- a/include/asm-ppc/fsl_serdes.h
+++ b/include/asm-ppc/fsl_serdes.h
@@ -3,9 +3,9 @@
#include <config.h>
-#define FSL_SERDES_CLK_100 0
-#define FSL_SERDES_CLK_125 1
-#define FSL_SERDES_CLK_150 3
+#define FSL_SERDES_CLK_100 (0 << 28)
+#define FSL_SERDES_CLK_125 (1 << 28)
+#define FSL_SERDES_CLK_150 (3 << 28)
#define FSL_SERDES_PROTO_SATA 0
#define FSL_SERDES_PROTO_PEX 1
#define FSL_SERDES_PROTO_PEX_X2 2
@@ -13,9 +13,9 @@
#define FSL_SERDES_VDD_1V 1
#ifdef CONFIG_FSL_SERDES
-extern void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd);
+extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
#else
-static void fsl_setup_serdes(u32 offset, char proto, char rfcks, char vdd) {}
+static void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd) {}
#endif /* CONFIG_FSL_SERDES */
#endif /* __FSL_SERDES_H */
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index c09b07d36..aade097fa 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -33,7 +33,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
- * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
+ * Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
@@ -122,17 +122,21 @@ typedef struct global_data {
phys_size_t ram_size; /* RAM size */
unsigned long reloc_off; /* Relocation Offset */
unsigned long reset_status; /* reset status register at boot */
+#if defined(CONFIG_MPC83XX)
+ unsigned long arbiter_event_attributes;
+ unsigned long arbiter_event_address;
+#endif
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
-#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
+#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif
#if defined(CONFIG_4xx)
u32 uart_clk;
#endif /* CONFIG_4xx */
-#if defined(CFG_GT_6426x)
+#if defined(CONFIG_SYS_GT_6426x)
unsigned int mirror_hack[16];
#endif
#if defined(CONFIG_A3000) || \
@@ -176,6 +180,7 @@ typedef struct global_data {
#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
+#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index ff183033c..df24a6e87 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -31,6 +31,7 @@
#include <asm/types.h>
#include <asm/fsl_i2c.h>
#include <asm/mpc8xxx_spi.h>
+#include <asm/fsl_lbc.h>
/*
* Local Access Window
@@ -343,50 +344,6 @@ typedef struct duart83xx {
} duart83xx_t;
/*
- * Local Bus Controller Registers
- */
-typedef struct lbus_bank {
- u32 br; /* Base Register */
- u32 or; /* Option Register */
-} lbus_bank_t;
-
-typedef struct lbus83xx {
- lbus_bank_t bank[8];
- u8 res0[0x28];
- u32 mar; /* UPM Address Register */
- u8 res1[0x4];
- u32 mamr; /* UPMA Mode Register */
- u32 mbmr; /* UPMB Mode Register */
- u32 mcmr; /* UPMC Mode Register */
- u8 res2[0x8];
- u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
- u32 mdr; /* UPM Data Register */
- u8 res3[0x4];
- u32 lsor; /* Special Operation Initiation Register */
- u32 lsdmr; /* SDRAM Mode Register */
- u8 res4[0x8];
- u32 lurt; /* UPM Refresh Timer */
- u32 lsrt; /* SDRAM Refresh Timer */
- u8 res5[0x8];
- u32 ltesr; /* Transfer Error Status Register */
- u32 ltedr; /* Transfer Error Disable Register */
- u32 lteir; /* Transfer Error Interrupt Register */
- u32 lteatr; /* Transfer Error Attributes Register */
- u32 ltear; /* Transfer Error Address Register */
- u8 res6[0xC];
- u32 lbcr; /* Configuration Register */
- u32 lcrr; /* Clock Ratio Register */
- u8 res7[0x8];
- u32 fmr; /* Flash Mode Register */
- u32 fir; /* Flash Instruction Register */
- u32 fcr; /* Flash Command Register */
- u32 fbar; /* Flash Block Addr Register */
- u32 fpar; /* Flash Page Addr Register */
- u32 fbcr; /* Flash Byte Count Register */
- u8 res8[0xF08];
-} lbus83xx_t;
-
-/*
* DMA/Messaging Unit
*/
typedef struct dma83xx {
@@ -614,7 +571,7 @@ typedef struct immap {
u8 res2[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res3[0x900];
- lbus83xx_t lbus; /* Local Bus Controller Registers */
+ fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res4[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@@ -648,7 +605,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
- lbus83xx_t lbus; /* Local Bus Controller Registers */
+ fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@@ -683,7 +640,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
- lbus83xx_t lbus; /* Local Bus Controller Registers */
+ fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@@ -728,7 +685,7 @@ typedef struct immap {
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
- lbus83xx_t lbus; /* Local Bus Controller Registers */
+ fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi8xxx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
@@ -778,7 +735,7 @@ typedef struct immap {
u8 res4[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res5[0x900];
- lbus83xx_t lbus; /* Local Bus Controller Registers */
+ fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res6[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
@@ -817,7 +774,7 @@ typedef struct immap {
u8 res3[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res4[0x900];
- lbus83xx_t lbus; /* Local Bus Controller Registers */
+ fsl_lbus_t lbus; /* Local Bus Controller Registers */
u8 res5[0x2000];
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 559d6ea6c..e5046bef3 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -13,6 +13,7 @@
#include <asm/types.h>
#include <asm/fsl_i2c.h>
+#include <asm/fsl_lbc.h>
/*
* Local-Access Registers and ECM Registers(0x0000-0x2000)
@@ -1552,6 +1553,13 @@ typedef struct par_io {
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
+#ifdef CONFIG_MPC8536
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
+#else
+#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
+#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
+#endif
uint porbmsr; /* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
@@ -1561,7 +1569,8 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
-#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
+#define MPC85xx_PORDEVSR_PCI1 0x00800000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
@@ -1572,7 +1581,8 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */
-#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000020
+/* The 8544 RM says this is bit 26, but it's really bit 24 */
+#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
char res1[8];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
char res2[12];
@@ -1638,39 +1648,37 @@ typedef struct ccsr_gur {
char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
-#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
-
-#define CFG_MPC85xx_GUTS_OFFSET (0xE0000)
-#define CFG_MPC85xx_GUTS_ADDR (CFG_IMMR + CFG_MPC85xx_GUTS_OFFSET)
-#define CFG_MPC85xx_ECM_OFFSET (0x0000)
-#define CFG_MPC85xx_ECM_ADDR (CFG_IMMR + CFG_MPC85xx_ECM_OFFSET)
-#define CFG_MPC85xx_DDR_OFFSET (0x2000)
-#define CFG_MPC85xx_DDR_ADDR (CFG_IMMR + CFG_MPC85xx_DDR_OFFSET)
-#define CFG_MPC85xx_DDR2_OFFSET (0x6000)
-#define CFG_MPC85xx_DDR2_ADDR (CFG_IMMR + CFG_MPC85xx_DDR2_OFFSET)
-#define CFG_MPC85xx_LBC_OFFSET (0x5000)
-#define CFG_MPC85xx_LBC_ADDR (CFG_IMMR + CFG_MPC85xx_LBC_OFFSET)
-#define CFG_MPC85xx_PCIX_OFFSET (0x8000)
-#define CFG_MPC85xx_PCIX_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX_OFFSET)
-#define CFG_MPC85xx_PCIX2_OFFSET (0x9000)
-#define CFG_MPC85xx_PCIX2_ADDR (CFG_IMMR + CFG_MPC85xx_PCIX2_OFFSET)
-#define CFG_MPC85xx_SATA1_OFFSET (0x18000)
-#define CFG_MPC85xx_SATA1_ADDR (CFG_IMMR + CFG_MPC85xx_SATA1_OFFSET)
-#define CFG_MPC85xx_SATA2_OFFSET (0x19000)
-#define CFG_MPC85xx_SATA2_ADDR (CFG_IMMR + CFG_MPC85xx_SATA2_OFFSET)
-#define CFG_MPC85xx_L2_OFFSET (0x20000)
-#define CFG_MPC85xx_L2_ADDR (CFG_IMMR + CFG_MPC85xx_L2_OFFSET)
-#define CFG_MPC85xx_DMA_OFFSET (0x21000)
-#define CFG_MPC85xx_DMA_ADDR (CFG_IMMR + CFG_MPC85xx_DMA_OFFSET)
-#define CFG_MPC85xx_ESDHC_OFFSET (0x2e000)
-#define CFG_MPC85xx_ESDHC_ADDR (CFG_IMMR + CFG_MPC85xx_ESDHC_OFFSET)
-#define CFG_MPC85xx_PIC_OFFSET (0x40000)
-#define CFG_MPC85xx_PIC_ADDR (CFG_IMMR + CFG_MPC85xx_PIC_OFFSET)
-#define CFG_MPC85xx_CPM_OFFSET (0x80000)
-#define CFG_MPC85xx_CPM_ADDR (CFG_IMMR + CFG_MPC85xx_CPM_OFFSET)
-#define CFG_MPC85xx_SERDES1_OFFSET (0xE3000)
-#define CFG_MPC85xx_SERDES1_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
-#define CFG_MPC85xx_SERDES2_OFFSET (0xE3100)
-#define CFG_MPC85xx_SERDES2_ADDR (CFG_IMMR + CFG_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000)
+#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
+#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000)
+#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
+#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000)
+#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
+#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000)
+#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000)
+#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000)
+#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
+#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000)
+#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000)
+#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
+#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000)
+#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
+#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000)
+#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
+#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000)
+#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
+#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000)
+#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000)
+#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
+#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000)
+#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000)
+#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100)
+#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#endif /*__IMMAP_85xx__*/
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 03a25c794..df28c0f2c 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1348,9 +1348,9 @@ typedef struct immap {
extern immap_t *immr;
-#define CFG_MPC86xx_DDR_OFFSET (0x2000)
-#define CFG_MPC86xx_DDR_ADDR (CFG_IMMR + CFG_MPC86xx_DDR_OFFSET)
-#define CFG_MPC86xx_DDR2_OFFSET (0x6000)
-#define CFG_MPC86xx_DDR2_ADDR (CFG_IMMR + CFG_MPC86xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000)
+#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
+#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000)
+#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
#endif /*__IMMAP_86xx__*/
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index c3496818f..64cb746b1 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -298,4 +298,9 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
}
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+ return (phys_addr_t)((unsigned long)vaddr);
+}
+
#endif
diff --git a/include/asm-ppc/iopin_8260.h b/include/asm-ppc/iopin_8260.h
index 21ed8c2ec..619f3a8ab 100644
--- a/include/asm-ppc/iopin_8260.h
+++ b/include/asm-ppc/iopin_8260.h
@@ -26,140 +26,140 @@ iopin_t;
extern __inline__ void
iopin_set_high(iopin_t *iopin)
{
- volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+ volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_low(iopin_t *iopin)
{
- volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+ volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_high(iopin_t *iopin)
{
- volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+ volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_low(iopin_t *iopin)
{
- volatile uint *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdata;
+ volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdata;
return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void
iopin_set_out(iopin_t *iopin)
{
- volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+ volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_in(iopin_t *iopin)
{
- volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+ volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_out(iopin_t *iopin)
{
- volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+ volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_in(iopin_t *iopin)
{
- volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdira;
+ volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdira;
return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void
iopin_set_odr(iopin_t *iopin)
{
- volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+ volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_act(iopin_t *iopin)
{
- volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+ volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_odr(iopin_t *iopin)
{
- volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+ volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_act(iopin_t *iopin)
{
- volatile uint *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_podra;
+ volatile uint *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_podra;
return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void
iopin_set_ded(iopin_t *iopin)
{
- volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+ volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_gen(iopin_t *iopin)
{
- volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+ volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_ded(iopin_t *iopin)
{
- volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+ volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_gen(iopin_t *iopin)
{
- volatile uint *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_ppara;
+ volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_ppara;
return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void
iopin_set_opt2(iopin_t *iopin)
{
- volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+ volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void
iopin_set_opt1(iopin_t *iopin)
{
- volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+ volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint
iopin_is_opt2(iopin_t *iopin)
{
- volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+ volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint
iopin_is_opt1(iopin_t *iopin)
{
- volatile uint *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_psora;
+ volatile uint *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_psora;
return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
diff --git a/include/asm-ppc/iopin_85xx.h b/include/asm-ppc/iopin_85xx.h
index daddb554d..0f07ba355 100644
--- a/include/asm-ppc/iopin_85xx.h
+++ b/include/asm-ppc/iopin_85xx.h
@@ -23,121 +23,121 @@ typedef struct {
extern __inline__ void iopin_set_high (iopin_t * iopin)
{
- volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_low (iopin_t * iopin)
{
- volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
datp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_high (iopin_t * iopin)
{
- volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return (datp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_low (iopin_t * iopin)
{
- volatile uint *datp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
+ volatile uint *datp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdata;
return ((datp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_out (iopin_t * iopin)
{
- volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_in (iopin_t * iopin)
{
- volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
dirp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_out (iopin_t * iopin)
{
- volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return (dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_in (iopin_t * iopin)
{
- volatile uint *dirp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
+ volatile uint *dirp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.pdira;
return ((dirp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_odr (iopin_t * iopin)
{
- volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_act (iopin_t * iopin)
{
- volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
odrp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_odr (iopin_t * iopin)
{
- volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return (odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_act (iopin_t * iopin)
{
- volatile uint *odrp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
+ volatile uint *odrp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.podra;
return ((odrp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_ded (iopin_t * iopin)
{
- volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_gen (iopin_t * iopin)
{
- volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
parp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_ded (iopin_t * iopin)
{
- volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return (parp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_gen (iopin_t * iopin)
{
- volatile uint *parp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
+ volatile uint *parp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.ppara;
return ((parp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
extern __inline__ void iopin_set_opt2 (iopin_t * iopin)
{
- volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] |= (1 << (31 - iopin->pin));
}
extern __inline__ void iopin_set_opt1 (iopin_t * iopin)
{
- volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
sorp[iopin->port * 8] &= ~(1 << (31 - iopin->pin));
}
extern __inline__ uint iopin_is_opt2 (iopin_t * iopin)
{
- volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return (sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1;
}
extern __inline__ uint iopin_is_opt1 (iopin_t * iopin)
{
- volatile uint *sorp = &((ccsr_cpm_t *) CFG_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
+ volatile uint *sorp = &((ccsr_cpm_t *) CONFIG_SYS_MPC85xx_CPM_ADDR)->im_cpm_iop.psora;
return ((sorp[iopin->port * 8] >> (31 - iopin->pin)) & 1) ^ 1;
}
diff --git a/include/asm-ppc/iopin_8xx.h b/include/asm-ppc/iopin_8xx.h
index 1946eb24c..3a2a682f6 100644
--- a/include/asm-ppc/iopin_8xx.h
+++ b/include/asm-ppc/iopin_8xx.h
@@ -46,16 +46,16 @@ extern __inline__ void
iopin_set_high(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
*datp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+ volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
*datp |= (1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
*datp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
*datp |= (1 << (15 - iopin->pin));
}
}
@@ -64,16 +64,16 @@ extern __inline__ void
iopin_set_low(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
*datp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+ volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
*datp &= ~(1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
*datp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
*datp &= ~(1 << (15 - iopin->pin));
}
}
@@ -82,16 +82,16 @@ extern __inline__ uint
iopin_is_high(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
return (*datp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+ volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
return (*datp >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
return (*datp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
return (*datp >> (15 - iopin->pin)) & 1;
}
return 0;
@@ -101,16 +101,16 @@ extern __inline__ uint
iopin_is_low(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padat;
return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *datp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdat;
+ volatile uint *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat;
return ((*datp >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat;
return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *datp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddat;
+ volatile ushort *datp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat;
return ((*datp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
@@ -120,16 +120,16 @@ extern __inline__ void
iopin_set_out(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
*dirp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+ volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
*dirp |= (1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
*dirp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
*dirp |= (1 << (15 - iopin->pin));
}
}
@@ -138,16 +138,16 @@ extern __inline__ void
iopin_set_in(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
*dirp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+ volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
*dirp &= ~(1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
*dirp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
*dirp &= ~(1 << (15 - iopin->pin));
}
}
@@ -156,16 +156,16 @@ extern __inline__ uint
iopin_is_out(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
return (*dirp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+ volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
return (*dirp >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
return (*dirp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
return (*dirp >> (15 - iopin->pin)) & 1;
}
return 0;
@@ -175,16 +175,16 @@ extern __inline__ uint
iopin_is_in(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_padir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_padir;
return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *dirp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbdir;
+ volatile uint *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir;
return ((*dirp >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcdir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdir;
return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *dirp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pddir;
+ volatile ushort *dirp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddir;
return ((*dirp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
@@ -194,10 +194,10 @@ extern __inline__ void
iopin_set_odr(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+ volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
*odrp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+ volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
*odrp |= (1 << (31 - iopin->pin));
}
}
@@ -206,10 +206,10 @@ extern __inline__ void
iopin_set_act(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+ volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
*odrp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+ volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
*odrp &= ~(1 << (31 - iopin->pin));
}
}
@@ -218,10 +218,10 @@ extern __inline__ uint
iopin_is_odr(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+ volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
return (*odrp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+ volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
return (*odrp >> (31 - iopin->pin)) & 1;
}
return 0;
@@ -231,10 +231,10 @@ extern __inline__ uint
iopin_is_act(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_ioport.iop_paodr;
+ volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_paodr;
return ((*odrp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile ushort *odrp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbodr;
+ volatile ushort *odrp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr;
return ((*odrp >> (31 - iopin->pin)) & 1) ^ 1;
}
return 0;
@@ -244,16 +244,16 @@ extern __inline__ void
iopin_set_ded(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
*parp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+ volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
*parp |= (1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
*parp |= (1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
*parp |= (1 << (15 - iopin->pin));
}
}
@@ -262,16 +262,16 @@ extern __inline__ void
iopin_set_gen(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
*parp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+ volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
*parp &= ~(1 << (31 - iopin->pin));
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
*parp &= ~(1 << (15 - iopin->pin));
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
*parp &= ~(1 << (15 - iopin->pin));
}
}
@@ -280,16 +280,16 @@ extern __inline__ uint
iopin_is_ded(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
return (*parp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+ volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
return (*parp >> (31 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
return (*parp >> (15 - iopin->pin)) & 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
return (*parp >> (15 - iopin->pin)) & 1;
}
return 0;
@@ -299,16 +299,16 @@ extern __inline__ uint
iopin_is_gen(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTA) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_papar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_papar;
return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTB) {
- volatile uint *parp = &((immap_t *)CFG_IMMR)->im_cpm.cp_pbpar;
+ volatile uint *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar;
return ((*parp >> (31 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTC) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcpar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcpar;
return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
} else if (iopin->port == IOPIN_PORTD) {
- volatile ushort *parp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pdpar;
+ volatile ushort *parp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pdpar;
return ((*parp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
@@ -318,7 +318,7 @@ extern __inline__ void
iopin_set_opt2(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+ volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
*sorp |= (1 << (15 - iopin->pin));
}
}
@@ -327,7 +327,7 @@ extern __inline__ void
iopin_set_opt1(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+ volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
*sorp &= ~(1 << (15 - iopin->pin));
}
}
@@ -336,7 +336,7 @@ extern __inline__ uint
iopin_is_opt2(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+ volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
return (*sorp >> (15 - iopin->pin)) & 1;
}
return 0;
@@ -346,7 +346,7 @@ extern __inline__ uint
iopin_is_opt1(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *sorp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcso;
+ volatile ushort *sorp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcso;
return ((*sorp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
@@ -356,7 +356,7 @@ extern __inline__ void
iopin_set_falledge(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+ volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
*intp |= (1 << (15 - iopin->pin));
}
}
@@ -365,7 +365,7 @@ extern __inline__ void
iopin_set_anyedge(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+ volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
*intp &= ~(1 << (15 - iopin->pin));
}
}
@@ -374,7 +374,7 @@ extern __inline__ uint
iopin_is_falledge(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+ volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
return (*intp >> (15 - iopin->pin)) & 1;
}
return 0;
@@ -384,7 +384,7 @@ extern __inline__ uint
iopin_is_anyedge(iopin_t *iopin)
{
if (iopin->port == IOPIN_PORTC) {
- volatile ushort *intp = &((immap_t *)CFG_IMMR)->im_ioport.iop_pcint;
+ volatile ushort *intp = &((immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcint;
return ((*intp >> (15 - iopin->pin)) & 1) ^ 1;
}
return 0;
diff --git a/include/asm-ppc/ppc4xx-ebc.h b/include/asm-ppc/ppc4xx-ebc.h
index d180e045f..9680f70d6 100644
--- a/include/asm-ppc/ppc4xx-ebc.h
+++ b/include/asm-ppc/ppc4xx-ebc.h
@@ -35,7 +35,38 @@
#define CONFIG_EBC_PPC4xx_IBM_VER1
#endif
+/*
+ * Define the max number of EBC banks (chip selects)
+ */
+#if defined(CONFIG_405CR) || defined(CONFIG_405GP) || \
+ defined(CONFIG_405EZ) || \
+ defined(CONFIG_440GP) || defined(CONFIG_440GX)
+#define EBC_NUM_BANKS 8
+#endif
+
+#if defined(CONFIG_405EP)
+#define EBC_NUM_BANKS 5
+#endif
+
+#if defined(CONFIG_405EX) || \
+ defined(CONFIG_460SX)
+#define EBC_NUM_BANKS 4
+#endif
+
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define EBC_NUM_BANKS 6
+#endif
+
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
+#define EBC_NUM_BANKS 3
+#endif
+
/* Bank Configuration Register */
+#define EBC_BXCR(n) (n)
+#define EBC_BXCR_BANK_SIZE(n) (0x100000 << (((n) & EBC_BXCR_BS_MASK) >> 17))
+
#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF)
#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(u32, n)) & EBC_BXCR_BAS_MASK))
#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7)
diff --git a/include/asm-ppc/ppc4xx-isram.h b/include/asm-ppc/ppc4xx-isram.h
new file mode 100644
index 000000000..d6d17ac96
--- /dev/null
+++ b/include/asm-ppc/ppc4xx-isram.h
@@ -0,0 +1,75 @@
+
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PPC4xx_ISRAM_H_
+#define _PPC4xx_ISRAM_H_
+
+/*
+ * Internal SRAM
+ */
+#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
+#define ISRAM0_DCR_BASE 0x380
+#else
+#define ISRAM0_DCR_BASE 0x020
+#endif
+#define ISRAM0_SB0CR (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
+#define ISRAM0_SB1CR (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
+#define ISRAM0_SB2CR (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
+#define ISRAM0_SB3CR (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
+#define ISRAM0_BEAR (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
+#define ISRAM0_BESR0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
+#define ISRAM0_BESR1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
+#define ISRAM0_PMEG (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
+#define ISRAM0_CID (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
+#define ISRAM0_REVID (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
+#define ISRAM0_DPC (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define ISRAM1_DCR_BASE 0x0B0
+#define ISRAM1_SB0CR (ISRAM1_DCR_BASE+0x00) /* SRAM1 bank config 0*/
+#define ISRAM1_BEAR (ISRAM1_DCR_BASE+0x04) /* SRAM1 bus error addr reg */
+#define ISRAM1_BESR0 (ISRAM1_DCR_BASE+0x05) /* SRAM1 bus error status reg 0 */
+#define ISRAM1_BESR1 (ISRAM1_DCR_BASE+0x06) /* SRAM1 bus error status reg 1 */
+#define ISRAM1_PMEG (ISRAM1_DCR_BASE+0x07) /* SRAM1 power management */
+#define ISRAM1_CID (ISRAM1_DCR_BASE+0x08) /* SRAM1 bus core id reg */
+#define ISRAM1_REVID (ISRAM1_DCR_BASE+0x09) /* SRAM1 bus revision id reg */
+#define ISRAM1_DPC (ISRAM1_DCR_BASE+0x0a) /* SRAM1 data parity check reg */
+#endif /* CONFIG_460EX || CONFIG_460GT */
+
+/*
+ * L2 Cache
+ */
+#if defined (CONFIG_440GX) || \
+ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
+#define L2_CACHE_BASE 0x030
+#define L2_CACHE_CFG (L2_CACHE_BASE+0x00) /* L2 Cache Config */
+#define L2_CACHE_CMD (L2_CACHE_BASE+0x01) /* L2 Cache Command */
+#define L2_CACHE_ADDR (L2_CACHE_BASE+0x02) /* L2 Cache Address */
+#define L2_CACHE_DATA (L2_CACHE_BASE+0x03) /* L2 Cache Data */
+#define L2_CACHE_STAT (L2_CACHE_BASE+0x04) /* L2 Cache Status */
+#define L2_CACHE_CVER (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
+#define L2_CACHE_SNP0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
+#define L2_CACHE_SNP1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
+#endif /* CONFIG_440GX */
+
+#endif /* _PPC4xx_ISRAM_H_ */
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index 0174d6235..98faced36 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -29,6 +29,7 @@
/*
* SDRAM Controller
*/
+
/*
* XXX - ToDo: Revisit file to change all these lower case defines into
* upper case. Also needs to be done in the controller setup code too
@@ -256,6 +257,7 @@
#define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
#define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
+#if !defined(CONFIG_405EX)
/*
* Memory queue defines
*/
@@ -270,8 +272,11 @@
#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1HB_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1HB_WRCL 0x00000080 /* MCIF Cycle Limit 1 - Bits 22..24 */
+#define SDRAM_CONF1HB_MASK 0x0000F380 /* RPLM & WRCL mask */
#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
@@ -282,8 +287,10 @@
#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */
#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */
#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */
+#define SDRAM_CONF1LL_RPLM 0x00001000 /* Read Passing Limit 1 - Bits 16..19 */
#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */
#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */
+#define SDRAM_CONF1LL_MASK 0x0000F000 /* RPLM mask */
#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
@@ -293,7 +300,6 @@
#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
-#if !defined(CONFIG_405EX)
/*
* Memory Bank 0-7 configuration
*/
@@ -1401,4 +1407,18 @@
#endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */
+#ifndef __ASSEMBLY__
+/*
+ * Prototypes
+ */
+void inline blank_string(int size);
+inline void ppc4xx_ibm_ddr2_register_dump(void);
+u32 mfdcr_any(u32);
+void mtdcr_any(u32, u32);
+u32 ddr_wrdtr(u32);
+u32 ddr_clktr(u32);
+void spd_ddr_init_hang(void);
+u32 DQS_autocalibration(void);
+#endif /* __ASSEMBLY__ */
+
#endif /* _PPC4xx_SDRAM_H_ */
diff --git a/include/asm-ppc/status_led.h b/include/asm-ppc/status_led.h
index eb81f371c..037570993 100644
--- a/include/asm-ppc/status_led.h
+++ b/include/asm-ppc/status_led.h
@@ -24,7 +24,7 @@ typedef unsigned long led_id_t;
static inline void __led_init (led_id_t mask, int state)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#ifdef STATUS_LED_PAR
immr->STATUS_LED_PAR &= ~mask;
@@ -51,12 +51,12 @@ static inline void __led_init (led_id_t mask, int state)
static inline void __led_toggle (led_id_t mask)
{
- ((immap_t *) CFG_IMMR)->STATUS_LED_DAT ^= mask;
+ ((immap_t *) CONFIG_SYS_IMMR)->STATUS_LED_DAT ^= mask;
}
static inline void __led_set (led_id_t mask, int state)
{
- volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index 54ac01d36..745190584 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -111,6 +111,12 @@ typedef struct bd_info {
#ifdef CONFIG_HAS_ETH3
unsigned char bi_enet3addr[6];
#endif
+#ifdef CONFIG_HAS_ETH4
+ unsigned char bi_enet4addr[6];
+#endif
+#ifdef CONFIG_HAS_ETH5
+ unsigned char bi_enet5addr[6];
+#endif
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-19 17:32:58 +0000