diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-nios2/io.h | 59 | ||||
| -rw-r--r-- | include/configs/PK1C20.h | 43 | ||||
| -rw-r--r-- | include/nios2-epcs.h | 71 | ||||
| -rw-r--r-- | include/nios2-io.h | 31 |
4 files changed, 169 insertions, 35 deletions
diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index c2c8ffcc3..b16a98865 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -29,8 +29,61 @@ extern unsigned char inb (unsigned char *port); extern unsigned short inw (unsigned short *port); extern unsigned inl (unsigned port); -extern void outb (unsigned char val, unsigned char *port); -extern void outw (unsigned short val, unsigned short *port); -extern void outl (unsigned val, unsigned port); + +#define readb(addr)\ + ({unsigned char val;\ + asm volatile( "ldbio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readw(addr)\ + ({unsigned short val;\ + asm volatile( "ldhio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define readl(addr)\ + ({unsigned long val;\ + asm volatile( "ldwio %0, 0(%1)" :"=r"(val) : "r" (addr)); val;}) +#define writeb(addr,val)\ + asm volatile ("stbio %0, 0(%1)" : : "r" (addr), "r" (val)) +#define writew(addr,val)\ + asm volatile ("sthio %0, 0(%1)" : : "r" (addr), "r" (val)) +#define writel(addr,val)\ + asm volatile ("stwio %0, 0(%1)" : : "r" (addr), "r" (val)) + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(addr,val) writeb(addr,val) +#define outw(addr,val) writew(addr,val) +#define outl(addr,val) writel(addr,val) + +static inline void insb (unsigned long port, void *dst, unsigned long count) +{ + unsigned char *p = dst; + while (count--) *p++ = inb (port); +} +static inline void insw (unsigned long port, void *dst, unsigned long count) +{ + unsigned short *p = dst; + while (count--) *p++ = inw (port); +} +static inline void insl (unsigned long port, void *dst, unsigned long count) +{ + unsigned long *p = dst; + while (count--) *p++ = inl (port); +} + +static inline void outsb (unsigned long port, const void *src, unsigned long count) +{ + const unsigned char *p = src; + while (count--) outb (*p++, port); +} + +static inline void outsw (unsigned long port, const void *src, unsigned long count) +{ + const unsigned short *p = src; + while (count--) outw (*p++, port); +} +static inline void outsl (unsigned long port, const void *src, unsigned long count) +{ + const unsigned long *p = src; + while (count--) outl (*p++, port); +} #endif /* __ASM_NIOS2_IO_H_ */ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index 865c69b5b..91e95186a 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -52,7 +52,7 @@ #define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ #define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ #define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */ -#define CFG_SRAM_SIZE 0x00200000 /* 2 MByte */ +#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ /*------------------------------------------------------------------------ * MEMORY ORGANIZATION @@ -107,6 +107,14 @@ #define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ /*------------------------------------------------------------------------ + * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for + * epcs device access is enabled. The base address is the epcs + * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. + * The register base is currently at offset 0x400 from the memory base. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */ + +/*------------------------------------------------------------------------ * DEBUG *----------------------------------------------------------------------*/ #undef CONFIG_ROM_STUBS /* Stubs not in ROM */ @@ -173,6 +181,36 @@ #include <cmd_confdefs.h> /*------------------------------------------------------------------------ + * COMPACT FLASH + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#define CONFIG_IDE_PREINIT /* Implement id_preinit */ +#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x00900800 /* ATA base addr */ +#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */ +#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */ +#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */ +#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */ +#define CFG_ATA_STRIDE 4 /* Width betwix addrs */ +#define CONFIG_DOS_PARTITION + +/* Board-specific cf regs */ +#define CFG_CF_PRESENT 0x00900880 /* CF Present PIO base */ +#define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ +#define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ + +#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ + +/*------------------------------------------------------------------------ + * JFFS2 + *----------------------------------------------------------------------*/ +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#define CFG_JFFS_CUSTOM_PART /* board defined part */ +#endif + +/*------------------------------------------------------------------------ * MISC *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* Provide extended help*/ @@ -185,4 +223,7 @@ #define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ #define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + #endif /* __CONFIG_H */ diff --git a/include/nios2-epcs.h b/include/nios2-epcs.h new file mode 100644 index 000000000..2c9522cfd --- /dev/null +++ b/include/nios2-epcs.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt@psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera Nios-II EPCS Controller Core interfaces + ************************************************************************/ + +#ifndef __NIOS2_EPCS_H__ +#define __NIOS2_EPCS_H__ + +typedef struct epcs_devinfo_t { + const char *name; /* Device name */ + unsigned char id; /* Device silicon id */ + unsigned char size; /* Total size log2(bytes)*/ + unsigned char num_sects; /* Number of sectors */ + unsigned char sz_sect; /* Sector size log2(bytes) */ + unsigned char sz_page; /* Page size log2(bytes) */ + unsigned char prot_mask; /* Protection mask */ +}epcs_devinfo_t; + +/* Returns the devinfo struct if EPCS device is found; + * NULL otherwise. + */ +extern epcs_devinfo_t *epcs_dev_find (void); + +/* Returns the number of bytes used by config data. + * Negative on error. + */ +extern int epcs_cfgsz (void); + +/* Erase sectors 'start' to 'end' - return zero on success + */ +extern int epcs_erase (unsigned start, unsigned end); + +/* Read 'cnt' bytes from device offset 'off' into buf at 'addr' + * Zero return on success + */ +extern int epcs_read (ulong addr, ulong off, ulong cnt); + +/* Write 'cnt' bytes to device offset 'off' from buf at 'addr'. + * Zero return on success + */ +extern int epcs_write (ulong addr, ulong off, ulong cnt); + +/* Verify 'cnt' bytes at device offset 'off' comparing with buf + * at 'addr'. On failure, write first invalid offset to *err. + * Zero return on success + */ +extern int epcs_verify (ulong addr, ulong off, ulong cnt, ulong *err); + +#endif /* __NIOS2_EPCS_H__ */ diff --git a/include/nios2-io.h b/include/nios2-io.h index d2aeabb94..d5c8652d5 100644 --- a/include/nios2-io.h +++ b/include/nios2-io.h @@ -137,37 +137,6 @@ typedef volatile struct nios_spi_t { #define NIOS_SPI_SSO (1 << 10) /* override SS_n output */ /*------------------------------------------------------------------------ - * ASMI - *----------------------------------------------------------------------*/ -typedef volatile struct nios_asmi_t { - unsigned rxdata; /* Rx data reg */ - unsigned txdata; /* Tx data reg */ - unsigned status; /* Status reg */ - unsigned control; /* Control reg */ - unsigned reserved; - unsigned slavesel; /* Slave select */ - unsigned endofpacket; /* End-of-packet reg */ -}nios_asmi_t; - -/* status register */ -#define NIOS_ASMI_ROE (1 << 3) /* rx overrun */ -#define NIOS_ASMI_TOE (1 << 4) /* tx overrun */ -#define NIOS_ASMI_TMT (1 << 5) /* tx empty */ -#define NIOS_ASMI_TRDY (1 << 6) /* tx ready */ -#define NIOS_ASMI_RRDY (1 << 7) /* rx ready */ -#define NIOS_ASMI_E (1 << 8) /* exception */ -#define NIOS_ASMI_EOP (1 << 9) /* eop detected */ - -/* control register */ -#define NIOS_ASMI_IROE (1 << 3) /* rx overrun int ena */ -#define NIOS_ASMI_ITOE (1 << 4) /* tx overrun int ena */ -#define NIOS_ASMI_ITRDY (1 << 6) /* tx ready int ena */ -#define NIOS_ASMI_IRRDY (1 << 7) /* rx ready int ena */ -#define NIOS_ASMI_IE (1 << 8) /* exception int ena */ -#define NIOS_ASMI_IEOP (1 << 9) /* rx eop int ena */ -#define NIOS_ASMI_SSO (1 << 10) /* slave select enable */ - -/*------------------------------------------------------------------------ * JTAG UART *----------------------------------------------------------------------*/ typedef volatile struct nios_jtag_t { |