diff options
author | Vijay Purushothaman <vijay.a.purushothaman@intel.com> | 2012-08-17 18:06:52 +0530 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-08-21 09:30:29 +0200 |
commit | 4fc76adf313f2792b7438f9372321ce3ea66c6c2 (patch) | |
tree | f9645fa65a9ef761caa34a33044400282eeac776 /lib/intel_chipset.h | |
parent | 082826de6c66ff76c444434cd56aaf6df80027b3 (diff) |
tools: Added intel_dpio_read and intel_dpio_write
In Valleyview the DPLL and lane control registers are accessible only
through side band fabric called DPIO. Added two tools to read and write
registers residing in this space.
v2: Moved the core read/write functions to lib/intel_dpio.c based on
Ben's feedback
Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'lib/intel_chipset.h')
-rwxr-xr-x | lib/intel_chipset.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h index a229ea17..9dd4c94c 100755 --- a/lib/intel_chipset.h +++ b/lib/intel_chipset.h @@ -196,6 +196,8 @@ dev == PCI_CHIP_IVYBRIDGE_S_GT2 || \ dev == PCI_CHIP_VALLEYVIEW_PO) +#define IS_VALLEYVIEW(devid) (devid == PCI_CHIP_VALLEYVIEW_PO) + #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ devid == PCI_CHIP_HASWELL_M_GT1 || \ devid == PCI_CHIP_HASWELL_S_GT1 || \ |