diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-04-03 18:29:46 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-04-04 13:50:11 +0300 |
| commit | 452e8776788f02b9425bcbaf9533081479a5cc51 (patch) | |
| tree | ac90313a70b814b61272deb49c7640026c3b7df0 /lib/rendercopy_i915.c | |
| parent | f43bb29c3e29143d8ad5fc70b82eccf5749d3958 (diff) | |
lib/rendercopy: Assert that buffer dimensions/stride are acceptable
Sprinkle some asserts into rendercopy to make sure we don't try
to exceed the render engine surface size/stride limitations.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'lib/rendercopy_i915.c')
| -rw-r--r-- | lib/rendercopy_i915.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c index b28fa98d..1baa7a1b 100644 --- a/lib/rendercopy_i915.c +++ b/lib/rendercopy_i915.c @@ -87,6 +87,11 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, { #define TEX_COUNT 1 uint32_t format_bits, tiling_bits = 0; + + igt_assert_lte(src->stride, 8192); + igt_assert_lte(igt_buf_width(src), 2048); + igt_assert_lte(igt_buf_height(src), 2048); + if (src->tiling != I915_TILING_NONE) tiling_bits = MS3_TILED_SURFACE; if (src->tiling == I915_TILING_Y) @@ -123,6 +128,10 @@ void gen3_render_copyfunc(struct intel_batchbuffer *batch, uint32_t tiling_bits = 0; uint32_t format_bits; + igt_assert_lte(dst->stride, 8192); + igt_assert_lte(igt_buf_width(dst), 2048); + igt_assert_lte(igt_buf_height(dst), 2048); + switch (dst->bpp) { case 8: format_bits = COLR_BUF_8BIT; break; case 16: format_bits = COLR_BUF_RGB565; break; |