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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2016-06-29 12:11:28 +0100 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2016-06-30 23:06:51 +0100 |
| commit | 2aa3dc83399a16588ba06ec1718ed709f55bb8d9 (patch) | |
| tree | d9b2c4550481d9375298ceb79fe7cf214cae3f08 /tools/intel_reg_checker.c | |
| parent | e63f1544ff033f8b8b5e83e16cb0e60e65a04c7d (diff) | |
intel_chipset: Replace lookup of GT size with computation
Instead of a large if-chain for matching devid to GT, we can just
compute it directly from the encoded devid.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'tools/intel_reg_checker.c')
| -rw-r--r-- | tools/intel_reg_checker.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c index 2d6da70c..6bde63ec 100644 --- a/tools/intel_reg_checker.c +++ b/tools/intel_reg_checker.c @@ -162,16 +162,17 @@ check_gt_mode(void) if (gen == 6) check_perf_bit(gt_mode, 8, "Full Rate Sampler Disable", false); - /* For DevSmallGT, this bit must be set, which means disable - * hashing. - */ - if (devid == PCI_CHIP_SANDYBRIDGE_GT1 || - devid == PCI_CHIP_SANDYBRIDGE_M_GT1) - check_bit(gt_mode, 6, "WIZ Hashing disable", true); - else if (gen == 6) - check_perf_bit(gt_mode, 6, "WIZ Hashing disable", false); - if (gen == 6) { + /* For DevSmallGT, this bit must be set, which means disable + * hashing. + */ + if (intel_gt(devid) == 0) + check_bit(gt_mode, 6, + "WIZ Hashing disable", true); + else + check_perf_bit(gt_mode, 6, + "WIZ Hashing disable", false); + check_perf_bit(gt_mode, 5, "TD Four Row Dispatch Disable", false); check_perf_bit(gt_mode, 4, "Full Size URB Disable", false); |