skl_compute_wrpll: Prefer even dividers

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/tools/skl_compute_wrpll.c b/tools/skl_compute_wrpll.c
index a3a6e587..55f2df4c 100644
--- a/tools/skl_compute_wrpll.c
+++ b/tools/skl_compute_wrpll.c
@@ -431,6 +431,13 @@ skl_ddi_calculate_wrpll2(int clock /* in Hz */,
 						      dco_freq,
 						      p);
 			}
+
+			/*
+			 * If a solution is found with an even divider, prefer
+			 * this one.
+			 */
+			if (d == 0 && ctx.p)
+				break;
 		}
 	}