Pass dimm parameters to populate populate controller options

Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>

4 files changed, 7 insertions, 87 deletions

diff --git a/cpu/mpc8xxx/ddr/ddr.h b/cpu/mpc8xxx/ddr/ddr.h
index 0d79be322..9ffd5485c 100644
--- a/cpu/mpc8xxx/ddr/ddr.h
+++ b/cpu/mpc8xxx/ddr/ddr.h
@@ -10,8 +10,8 @@
 #define FSL_DDR_MAIN_H
 
 #include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
 
-#include "ddr1_2_dimm_params.h"
 #include "common_timing_params.h"
 
 /*
@@ -71,6 +71,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 				      unsigned int number_of_dimms);
 extern unsigned int populate_memctl_options(int all_DIMMs_registered,
 				memctl_options_t *popts,
+				dimm_params_t *pdimm,
 				unsigned int ctrl_num);
 
 extern unsigned int mclk_to_picos(unsigned int mclk);
diff --git a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h b/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
deleted file mode 100644
index c794eedfe..000000000
--- a/cpu/mpc8xxx/ddr/ddr1_2_dimm_params.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#ifndef DDR2_DIMM_PARAMS_H
-#define DDR2_DIMM_PARAMS_H
-
-/* Parameters for a DDR2 dimm computed from the SPD */
-typedef struct dimm_params_s {
-
-	/* DIMM organization parameters */
-	char mpart[19];		/* guaranteed null terminated */
-
-	unsigned int n_ranks;
-	unsigned long long rank_density;
-	unsigned long long capacity;
-	unsigned int data_width;
-	unsigned int primary_sdram_width;
-	unsigned int ec_sdram_width;
-	unsigned int registered_dimm;
-
-	/* SDRAM device parameters */
-	unsigned int n_row_addr;
-	unsigned int n_col_addr;
-	unsigned int edc_config;	/* 0 = none, 1 = parity, 2 = ECC */
-	unsigned int n_banks_per_sdram_device;
-	unsigned int burst_lengths_bitmask;	/* BL=4 bit 2, BL=8 = bit 3 */
-	unsigned int row_density;
-
-	/* used in computing base address of DIMMs */
-	unsigned long long base_address;
-
-	/* DIMM timing parameters */
-
-	/*
-	 * SDRAM clock periods
-	 * The range for these are 1000-10000 so a short should be sufficient
-	 */
-	unsigned int tCKmin_X_ps;
-	unsigned int tCKmin_X_minus_1_ps;
-	unsigned int tCKmin_X_minus_2_ps;
-	unsigned int tCKmax_ps;
-
-	/* SPD-defined CAS latencies */
-	unsigned int caslat_X;
-	unsigned int caslat_X_minus_1;
-	unsigned int caslat_X_minus_2;
-
-	unsigned int caslat_lowest_derated;	/* Derated CAS latency */
-
-	/* basic timing parameters */
-	unsigned int tRCD_ps;
-	unsigned int tRP_ps;
-	unsigned int tRAS_ps;
-
-	unsigned int tWR_ps;	/* maximum = 63750 ps */
-	unsigned int tWTR_ps;	/* maximum = 63750 ps */
-	unsigned int tRFC_ps;   /* max = 255 ns + 256 ns + .75 ns
-				       = 511750 ps */
-
-	unsigned int tRRD_ps;	/* maximum = 63750 ps */
-	unsigned int tRC_ps;	/* maximum = 254 ns + .75 ns = 254750 ps */
-
-	unsigned int refresh_rate_ps;
-
-	unsigned int tIS_ps;	/* byte 32, spd->ca_setup */
-	unsigned int tIH_ps;	/* byte 33, spd->ca_hold */
-	unsigned int tDS_ps;	/* byte 34, spd->data_setup */
-	unsigned int tDH_ps;	/* byte 35, spd->data_hold */
-	unsigned int tRTP_ps;	/* byte 38, spd->trtp */
-	unsigned int tDQSQ_max_ps;	/* byte 44, spd->tdqsq */
-	unsigned int tQHS_ps;	/* byte 45, spd->tqhs */
-} dimm_params_t;
-
-extern unsigned int ddr_compute_dimm_parameters(
-					 const generic_spd_eeprom_t *spd,
-					 dimm_params_t *pdimm,
-					 unsigned int dimm_number);
-
-#endif
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index d26c5c5c2..700b89717 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -319,7 +319,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
 			 */
 			populate_memctl_options(
 					timing_params[i].all_DIMMs_registered,
-					&pinfo->memctl_opts[i], i);
+					&pinfo->memctl_opts[i],
+					pinfo->dimm_params[i], i);
 		}
 
 	case STEP_ASSIGN_ADDRESSES:
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 6c2b43c0c..99b568566 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -13,10 +13,12 @@
 
 /* Board-specific functions defined in each board's ddr.c */
 extern void fsl_ddr_board_options(memctl_options_t *popts,
+		dimm_params_t *pdimm,
 		unsigned int ctrl_num);
 
 unsigned int populate_memctl_options(int all_DIMMs_registered,
 			memctl_options_t *popts,
+			dimm_params_t *pdimm,
 			unsigned int ctrl_num)
 {
 	unsigned int i;
@@ -191,7 +193,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 * controllers.
 	 */
 
-	fsl_ddr_board_options(popts, ctrl_num);
+	fsl_ddr_board_options(popts, pdimm, ctrl_num);
 
 	return 0;
 }