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AgeCommit message (Expand)Author
2010-01-05fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleaveDave Liu
2010-01-05fsl-ddr: add override for the Rtt_WrDave Liu
2010-01-05fsl-ddr: add the override for write levelingDave Liu
2010-01-05fsl-ddr: Fix power-down timing settingsDave Liu
2010-01-05ppc/8xxx: Remove is_fsl_pci_agentKumar Gala
2010-01-05ppc/8xxx: Don't use pci_cfg on FSL_CORENET platformsKumar Gala
2009-11-12fsl-ddr: Fix the chip-select interleaving issueDave Liu
2009-10-16mpc8xxx: improve LAW error messages when setting up DDRPaul Gortmaker
2009-09-24ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala
2009-09-15ppc/8xxx: Misc DDR related fixesKumar Gala
2009-09-08ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().Poonam Aggrwal
2009-09-08ppc/85xx/86xx: Device tree fixup for number of coresPoonam Aggrwal
2009-09-08ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal
2009-09-08ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala
2009-09-08ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala
2009-08-2885xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal
2009-08-2885xx: Added P1020 Processor Support.Poonam Aggrwal
2009-08-288xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal
2009-08-288xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal
2009-07-2285xx, 86xx: Add common board_add_ram_info()Peter Tyser
2009-07-01fsl_ddr: Fix DDR3 calculation of rank density with 8GB or moreTimur Tabi
2009-06-12fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BITKumar Gala
2009-03-30fsl-ddr: add the DDR3 SPD infrastructureDave Liu
2009-03-30fsl-ddr: Fix two bugs in the ddr infrastructureDave Liu
2009-02-16fsl-ddr: Allow system to boot if we have more than 4G of memoryKumar Gala
2009-02-16fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala
2009-01-23fsl-ddr: use the 1T timing as default configurationDave Liu
2009-01-23fsl-ddr: make the self refresh idle threshold configurableDave Liu
2009-01-23fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu
2009-01-23fsl-ddr: update the bit mask for DDR3 controllerDave Liu
2008-12-03fsl ddr skip interleaving if not supported.Ed Swarthout
2008-10-18Add debug information for DDR controller registersHaiying Wang
2008-10-18Check DDR interleaving modeHaiying Wang
2008-10-18Pass dimm parameters to populate populate controller optionsHaiying Wang
2008-10-18Make DDR interleaving mode work correctlyHaiying Wang
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
2008-09-13Coding style cleanup, update CHANGELOGWolfgang Denk
2008-09-07Fix compiler warning in mpc8xxx ddr codeKumar Gala
2008-08-27FSL DDR: Add DDR2 DIMM paramter supportKumar Gala
2008-08-27FSL DDR: Add DDR1 DIMM paramter supportKumar Gala
2008-08-27FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala
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