Merge branch 'master' of http://git.denx.de/u-boot

12 files changed, 218 insertions, 69 deletions

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 0d6a5fec9..75b45222b 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -70,6 +70,12 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
 		(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
 #endif
+#ifdef CONFIG_SYS_ACR_APARK	/* Arbiter address parking mode */
+		(ACR_APARK << ACR_APARK_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_PARKM	/* Arbiter parking master */
+		(ACR_PARKM << ACR_PARKM_SHIFT) |
+#endif
 		0;
 	__be32 acr_val =
 #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
@@ -78,6 +84,12 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
 		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
 #endif
+#ifdef CONFIG_SYS_ACR_APARK	/* Arbiter address parking mode */
+		(CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
+#endif
+#ifdef CONFIG_SYS_ACR_PARKM	/* Arbiter parking master */
+		(CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
+#endif
 		0;
 	__be32 spcr_mask =
 #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 0f611804a..44aaa9abc 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -29,6 +29,7 @@
 
 #include <common.h>
 #include <asm/processor.h>
+#include <asm/io.h>
 #include <i2c.h>
 #include <spd.h>
 #include <asm/mmu.h>
@@ -150,6 +151,14 @@ long int spd_sdram()
 	unsigned int ddrc_ecc_enable;
 	unsigned int pvr = get_pvr();
 
+	/*
+	 * First disable the memory controller (could be enabled
+	 * by the debugger)
+	 */
+	clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
+	sync();
+	isync();
+
 	/* Read SPD parameters with I2C */
 	CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
 #ifdef SPD_DEBUG
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 0041a60df..e0126d331 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -246,6 +246,7 @@ void cpu_init_f (void)
 #ifdef CONFIG_FSL_CORENET
 	corenet_tb_init();
 #endif
+	init_used_tlb_cams();
 }
 
 
@@ -357,6 +358,11 @@ int cpu_init_r(void)
 	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 		;
 
+#ifdef CONFIG_SYS_CACHE_STASHING
+	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
+	mtspr(SPRN_L2CSR1, (32 + 1));
+#endif
+
 	/* enable the cache */
 	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 
diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index de2dcac81..af0e78e07 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -197,6 +197,15 @@ static inline void ft_fixup_l2cache(void *blob)
 			goto next;
 		}
 
+#ifdef CONFIG_SYS_CACHE_STASHING
+		{
+			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+			if (reg)
+				fdt_setprop_cell(blob, l2_off, "cache-stash-id",
+					 (*reg * 2) + 32 + 1);
+		}
+#endif
+
 		fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
 		fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
 		fdt_setprop_cell(blob, l2_off, "cache-size", size);
@@ -252,6 +261,15 @@ static inline void ft_fixup_cache(void *blob)
 		fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 		fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 
+#ifdef CONFIG_SYS_CACHE_STASHING
+		{
+			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+			if (reg)
+				fdt_setprop_cell(blob, off, "cache-stash-id",
+					 (*reg * 2) + 32 + 0);
+		}
+#endif
+
 		/* i-side config */
 		isize = (l1cfg1 & 0x7ff) * 1024;
 		inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
@@ -279,6 +297,40 @@ void fdt_add_enet_stashing(void *fdt)
 	do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 }
 
+#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
+static void ft_fixup_clks(void *blob, const char *alias, unsigned long freq)
+{
+	const char *path = fdt_get_alias(blob, alias);
+
+	int off = fdt_path_offset(blob, path);
+
+	if (off >= 0) {
+		off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
+		if (off > 0)
+			printf("WARNING enable to set clock-frequency "
+				"for %s: %s\n", alias, fdt_strerror(off));
+	}
+}
+
+static void ft_fixup_dpaa_clks(void *blob)
+{
+	sys_info_t sysinfo;
+
+	get_sys_info(&sysinfo);
+	ft_fixup_clks(blob, "fman0", sysinfo.freqFMan[0]);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	ft_fixup_clks(blob, "fman1", sysinfo.freqFMan[1]);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_PME
+	ft_fixup_clks(blob, "pme", sysinfo.freqPME);
+#endif
+}
+#else
+#define ft_fixup_dpaa_clks(x)
+#endif
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	int off;
@@ -342,4 +394,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #if defined(CONFIG_FSL_ESDHC)
 	fdt_fixup_esdhc(blob, bd);
 #endif
+
+	ft_fixup_dpaa_clks(blob);
 }
diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 7626eb8e7..6530cb176 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -165,6 +165,9 @@ static void plat_mp_up(unsigned long bootpg)
 	e = find_law(bootpg);
 	out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
 
+	/* readback to sync write */
+	in_be32(&ccm->bstrar);
+
 	/* disable time base at the platform */
 	out_be32(&rcpm->ctbenrl, cpu_up_mask);
 
@@ -309,7 +312,7 @@ void setup_mp(void)
 		disable_tlb(i);
 
 		set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 			0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
 
 		memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 433ff0254..00c4c547f 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -99,6 +99,13 @@ __secondary_start_page:
 	slwi	r8,r4,5
 	add	r10,r3,r8
 
+#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+	slwi	r8,r4,1
+	addi	r8,r8,32
+	mtspr	L1CSR2,r8
+#endif
+
 #ifdef CONFIG_BACKSIDE_L2_CACHE
 	/* Enable/invalidate the L2 cache */
 	msync
@@ -110,6 +117,12 @@ __secondary_start_page:
 	and.	r1,r3,r2
 	bne	1b
 
+#ifdef CONFIG_SYS_CACHE_STASHING
+	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
+	addi	r3,r8,1
+	mtspr	SPRN_L2CSR1,r3
+#endif
+
 	lis	r3,CONFIG_SYS_INIT_L2CSR0@h
 	ori	r3,r3,CONFIG_SYS_INIT_L2CSR0@l
 	mtspr	SPRN_L2CSR0,r3
@@ -153,8 +166,8 @@ __secondary_start_page:
 	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
 	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 	mtspr	SPRN_MAS1,r11
-	oris	r11,r13,(MAS2_I)@h
-	ori	r11,r13,(MAS2_I)@l
+	oris	r11,r13,(MAS2_I|MAS2_G)@h
+	ori	r11,r13,(MAS2_I|MAS2_G)@l
 	mtspr	SPRN_MAS2,r11
 	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
 	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 795908240..2103e2edf 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -103,21 +103,21 @@ void get_sys_info (sys_info_t * sysInfo)
 
 #ifdef CONFIG_SYS_DPAA_PME
 	if (rcw_tmp & PME_CLK_SEL)
-		sysInfo->freqPME = freqCC_PLL[2] / 2;
-	else
 		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+	else
+		sysInfo->freqPME = freqCC_PLL[2] / 2;
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 	if (rcw_tmp & FM1_CLK_SEL)
-		sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
-	else
 		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+	else
+		sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
 #if (CONFIG_SYS_NUM_FMAN) == 2
 	if (rcw_tmp & FM2_CLK_SEL)
-		sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
-	else
 		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+	else
+		sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
 #endif
 #endif
 
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 6a865283d..7e60e67c3 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2009 Freescale Semiconductor.
+ * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
  * Copyright (C) 2003  Motorola,Inc.
  *
  * See file CREDITS for list of people who contributed to this
@@ -102,6 +102,12 @@ _start_e500:
 	 *
 	 */
 
+#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+	li	r2,(32 + 0)
+	mtspr	L1CSR2,r2
+#endif
+
 	lis	r2,L1CSR0_CPE@H	/* enable parity */
 	ori	r2,r2,L1CSR0_DCE
 	mtspr	L1CSR0,r2	/* enable L1 Dcache */
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index ea5deb297..b3037acea 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -56,12 +56,74 @@ void init_tlbs(void)
 }
 
 #ifndef CONFIG_NAND_SPL
+static inline void use_tlb_cam(u8 idx)
+{
+	int i = idx / 32;
+	int bit = idx % 32;
+
+	gd->used_tlb_cams[i] |= (1 << bit);
+}
+
+static inline void free_tlb_cam(u8 idx)
+{
+	int i = idx / 32;
+	int bit = idx % 32;
+
+	gd->used_tlb_cams[i] &= ~(1 << bit);
+}
+
+void init_used_tlb_cams(void)
+{
+	int i;
+	unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
+
+	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
+		gd->used_tlb_cams[i] = 0;
+
+	/* walk all the entries */
+	for (i = 0; i < num_cam; i++) {
+		u32 _mas1;
+
+		mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
+
+		asm volatile("tlbre;isync");
+		_mas1 = mfspr(MAS1);
+
+		/* if the entry isn't valid skip it */
+		if ((_mas1 & MAS1_VALID))
+			use_tlb_cam(i);
+	}
+}
+
+int find_free_tlbcam(void)
+{
+	int i;
+	u32 idx;
+
+	for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
+		idx = ffz(gd->used_tlb_cams[i]);
+
+		if (idx != 32)
+			break;
+	}
+
+	idx += i * 32;
+
+	if (idx >= CONFIG_SYS_NUM_TLBCAMS)
+		return -1;
+
+	return idx;
+}
+
 void set_tlb(u8 tlb, u32 epn, u64 rpn,
 	     u8 perms, u8 wimge,
 	     u8 ts, u8 esel, u8 tsize, u8 iprot)
 {
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
 
+	if (tlb == 1)
+		use_tlb_cam(esel);
+
 	_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
 	_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
 	_mas2 = FSL_BOOKE_MAS2(epn, wimge);
@@ -80,6 +142,8 @@ void disable_tlb(u8 esel)
 {
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
 
+	free_tlb_cam(esel);
+
 	_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
 	_mas1 = 0;
 	_mas2 = 0;
@@ -163,14 +227,10 @@ void init_addr_map(void)
 }
 #endif
 
-#ifndef CONFIG_SYS_DDR_TLB_START
-#define CONFIG_SYS_DDR_TLB_START 8
-#endif
-
 unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 {
+	int i;
 	unsigned int tlb_size;
-	unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
 	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
 	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
 	u64 size, memsize = (u64)memsize_in_meg << 20;
@@ -180,10 +240,14 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
 	/* Convert (4^max) kB to (2^max) bytes */
 	max_cam = max_cam * 2 + 10;
 
-	for (; size && ram_tlb_index < 16; ram_tlb_index++) {
+	for (i = 0; size && i < 8; i++) {
+		int ram_tlb_index = find_free_tlbcam();
 		u32 camsize = __ilog2_u64(size) & ~1U;
 		u32 align = __ilog2(ram_tlb_address) & ~1U;
 
+		if (ram_tlb_index == -1)
+			break;
+
 		if (align == -2) align = max_cam;
 		if (camsize > align)
 			camsize = align;
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 250504145..adc4f6ee3 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -188,12 +188,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 	 * The DDR3 spec has not tXARD,
 	 * we use the tXP instead of it.
 	 * tXP=max(3nCK, 7.5ns) for DDR3.
-	 * we use the tXP=6
 	 * spec has not the tAXPD, we use
 	 * tAXPD=8, need design to confirm.
 	 */
-	act_pd_exit_mclk = 6;
-	pre_pd_exit_mclk = 6;
+	int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+	act_pd_exit_mclk = picos_to_mclk(tXP);
+	/* Mode register MR0[A12] is '1' - fast exit */
+	pre_pd_exit_mclk = act_pd_exit_mclk;
 	taxpd_mclk = 8;
 	tmrd_mclk = 4;
 #else /* CONFIG_FSL_DDR2 */
@@ -575,18 +576,22 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 }
 
 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
-static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr)
+static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
+				const memctl_options_t *popts)
 {
 	unsigned short esdmode2 = 0;	/* Extended SDRAM mode 2 */
 	unsigned short esdmode3 = 0;	/* Extended SDRAM mode 3 */
 
 #if defined(CONFIG_FSL_DDR3)
-	unsigned int rtt_wr = 2;	/* 120 ohm Rtt_WR */
+	unsigned int rtt_wr = 0;	/* Rtt_WR - dynamic ODT off */
 	unsigned int srt = 0;	/* self-refresh temerature, normal range */
 	unsigned int asr = 0;	/* auto self-refresh disable */
 	unsigned int cwl = compute_cas_write_latency() - 5;
 	unsigned int pasr = 0;	/* partial array self refresh disable */
 
+	if (popts->rtt_override)
+		rtt_wr = popts->rtt_wr_override_value;
+
 	esdmode2 = (0
 		| ((rtt_wr & 0x3) << 9)
 		| ((srt & 0x1) << 7)
@@ -1001,8 +1006,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
 }
 
 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
-static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
-			       unsigned int wrlvl_en)
+static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
+				const memctl_options_t *popts)
 {
 	/*
 	 * First DQS pulse rising edge after margining mode
@@ -1029,8 +1034,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
 		/* tWL_DQSEN min = 25 nCK, we set it 32 */
 		wrlvl_dqsen = 0x5;
 		/*
-		 * Write leveling sample time at least need 14 clocks
-		 * due to tWLO = 9, we set it 15 clocks
+		 * Write leveling sample time at least need 6 clocks
+		 * higher than tWLO to allow enough time for progagation
+		 * delay and sampling the prime data bits.
 		 */
 		wrlvl_smpl = 0xf;
 		/*
@@ -1043,9 +1049,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr,
 		 * Write leveling start time
 		 * The value use for the DQS_ADJUST for the first sample
 		 * when write leveling is enabled.
-		 * we set it 1 clock delay
 		 */
 		wrlvl_start = 0x8;
+		/*
+		 * Override the write leveling sample and start time
+		 * according to specific board
+		 */
+		if (popts->wrlvl_override) {
+			wrlvl_smpl = popts->wrlvl_sample;
+			wrlvl_start = popts->wrlvl_start;
+		}
 	}
 
 	ddr->ddr_wrlvl_cntl = (0
@@ -1184,7 +1197,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			/* Don't set up boundaries for other CS
 			 * other than CS0, if bank interleaving
 			 * is enabled and not CS2+CS3 interleaved.
+			 * But we need to set the ODT_RD_CFG and
+			 * ODT_WR_CFG for CS1_CONFIG here.
 			 */
+			set_csn_config(i, ddr, popts, dimm_params);
 			break;
 		}
 
@@ -1321,7 +1337,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_sdram_cfg_2(ddr, popts);
 	set_ddr_sdram_mode(ddr, popts, common_dimm,
 				cas_latency, additive_latency);
-	set_ddr_sdram_mode_2(ddr);
+	set_ddr_sdram_mode_2(ddr, popts);
 	set_ddr_sdram_interval(ddr, popts, common_dimm);
 	set_ddr_data_init(ddr);
 	set_ddr_sdram_clk_cntl(ddr, popts);
@@ -1331,7 +1347,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_timing_cfg_5(ddr);
 
 	set_ddr_zq_cntl(ddr, zq_en);
-	set_ddr_wrlvl_cntl(ddr, wrlvl_en);
+	set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
 
 	set_ddr_sr_cntr(ddr, sr_it);
 
diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c
index 2e030c11a..3dcd33ddf 100644
--- a/cpu/mpc8xxx/ddr/options.c
+++ b/cpu/mpc8xxx/ddr/options.c
@@ -198,6 +198,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	 * meet the tQDSS under different loading.
 	 */
 	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 0;
 #endif
 
 	/*
diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c
index 9c7d92c4d..d53781b62 100644
--- a/cpu/mpc8xxx/pci_cfg.c
+++ b/cpu/mpc8xxx/pci_cfg.c
@@ -25,19 +25,14 @@
 #include <pci.h>
 
 struct pci_info {
-	u16	agent;
 	u16	cfg;
 };
 
-/* The agent field is a bit mask in which each bit represents the value of
- * cfg_host_agt[] signal and the bit is set of the given interface would be
- * in agent/end-point mode for the given interface.
- *
- * The same idea is true of the cfg field.  The bit will be set if the
- * interface would be enabled based on the value of cfg_IO_ports[] signal
+/* The cfg field is a bit mask in which each bit represents the value of
+ * cfg_IO_ports[] signal and the bit is set if the interface would be
+ * enabled based on the value of cfg_IO_ports[] signal
  *
  * On MPC86xx/PQ3 based systems:
- *   we extract cfg_host_agt from GUTS register PORBMSR
  *   we extract cfg_IO_ports from GUTS register PORDEVSR
  *
  * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems
@@ -48,7 +43,6 @@ struct pci_info {
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCI] = {
-		.agent = (1 << 0) | (1 << 2),
 		.cfg =   0,
 	},
 };
@@ -56,7 +50,6 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCI] = {
-		.agent = (1 << 0),
 		.cfg =   0,
 	},
 };
@@ -64,19 +57,15 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCI] = {
-		.agent = (1 << 6),
 		.cfg =   0,
 	},
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 5),
 		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7),
 	},
 	[LAW_TRGT_IF_PCIE_2] = {
-		.agent = (1 << 3),
 		.cfg =   (1 << 5) | (1 << 7),
 	},
 	[LAW_TRGT_IF_PCIE_3] = {
-		.agent = (1 << 1),
 		.cfg =   (1 << 7),
 	},
 };
@@ -84,20 +73,16 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCI] = {
-		.agent = (1 << 6),
 		.cfg =   0,
 	},
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 5),
 		.cfg =   (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
 			 (1 << 6) | (1 << 7),
 	},
 	[LAW_TRGT_IF_PCIE_2] = {
-		.agent = (1 << 3),
 		.cfg =   (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7),
 	},
 	[LAW_TRGT_IF_PCIE_3] = {
-		.agent = (1 << 1),
 		.cfg =   (1 << 6) | (1 << 7),
 	},
 };
@@ -105,16 +90,13 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCI_1] = {
-		.agent = (1 << 4) | (1 << 6),
 		.cfg =   0,
 	},
 	[LAW_TRGT_IF_PCI_2] = {
-		.agent = (1 << 4) | (1 << 6),
 		.cfg =   0,
 	},
 	/* PCI_2 is always host and we dont use iosel to determine enable/disable */
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 0) | (1 << 2),
 		.cfg =   (1 << 3) | (1 << 4) | (1 << 7),
 	},
 };
@@ -122,11 +104,9 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCI] = {
-		.agent = (1 << 0) | (1 << 4) | (1 << 6),
 		.cfg =   0,
 	},
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 0) | (1 << 2) | (1 << 4),
 		.cfg =   (1 << 3) | (1 << 4) | (1 << 7),
 	},
 };
@@ -134,7 +114,6 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 0) | (1 << 6),
 		.cfg =   (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) |
 			 (1 << 8) | (1 << 0xc) | (1 << 0xf),
 	},
@@ -143,16 +122,13 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5),
 		.cfg =   (1 << 2) | (1 << 3) | (1 << 7) |
 			 (1 << 0xb) | (1 << 0xc) | (1 << 0xf),
 	},
 	[LAW_TRGT_IF_PCIE_2] = {
-		.agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6),
 		.cfg =   (1 << 3) | (1 << 7),
 	},
 	[LAW_TRGT_IF_PCIE_3] = {
-		.agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6),
 		.cfg =   (1 << 7),
 	},
 };
@@ -160,15 +136,12 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCI_1] = {
-		.agent = (1 << 4) | (1 << 5) | (1 << 6),
 		.cfg =   0,
 	},
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 0) | (1 << 2) | (1 << 5),
 		.cfg =   (1 << 1) | (1 << 4),
 	},
 	[LAW_TRGT_IF_PCIE_2] = {
-		.agent = (1 << 0) | (1 << 1) | (1 << 4),
 		.cfg =   (1 << 0) | (1 << 4),
 	},
 };
@@ -176,7 +149,6 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = 0, /* we dont use agent on 8641 */
 		.cfg =   (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) |
 			 (1 << 7) | (1 << 0xe) | (1 << 0xf),
 	},
@@ -185,11 +157,9 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 0) | (1 << 1),
 		.cfg =   (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf),
 	},
 	[LAW_TRGT_IF_PCIE_2] = {
-		.agent = (1 << 0) | (1 << 2),
 		.cfg =   (1 << 0xe),
 	},
 };
@@ -197,29 +167,24 @@ static struct pci_info pci_config_info[] =
 static struct pci_info pci_config_info[] =
 {
 	[LAW_TRGT_IF_PCIE_1] = {
-		.agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5),
 		.cfg =   (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) |
 			 (1 << 0xd) | (1 << 0xe) | (1 << 0xf),
 	},
 	[LAW_TRGT_IF_PCIE_2] = {
-		.agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6),
 		.cfg =   (1 << 2) | (1 << 0xe),
 	},
 	[LAW_TRGT_IF_PCIE_3] = {
-		.agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6),
 		.cfg =   (1 << 2) | (1 << 4),
 	},
 };
+#elif defined(CONFIG_FSL_CORENET)
 #else
 #error Need to define pci_config_info for processor
 #endif
 
-int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent)
-{
-	return ((1 << host_agent) & pci_config_info[trgt].agent);
-}
-
+#ifndef CONFIG_FSL_CORENET
 int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel)
 {
 	return ((1 << io_sel) & pci_config_info[trgt].cfg);
 }
+#endif