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path: root/board/esd/pci405/pci405.c
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Diffstat (limited to 'board/esd/pci405/pci405.c')
-rw-r--r--board/esd/pci405/pci405.c88
1 files changed, 19 insertions, 69 deletions
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index f740d595b..42774ad20 100644
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -27,6 +27,7 @@
#include <malloc.h>
#include <pci.h>
#include <asm/4xx_pci.h>
+#include <asm/io.h>
#include "pci405.h"
@@ -34,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);/*cmd_boot.c*/
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
unsigned long fpga_done_state(void);
unsigned long fpga_init_state(void);
@@ -57,11 +58,11 @@ const unsigned char fpgadata[] =
*/
#include "../common/fpga.c"
-#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE)
-#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12)
+#define FPGA_DONE_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
-#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT)
-#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12)
+#define FPGA_INIT_STATE_V11 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in_be32((void*)GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
int board_revision(void)
@@ -78,10 +79,10 @@ int board_revision(void)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00100200);
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00100200);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
udelay(1000); /* wait some time before reading input */
- value = in32(GPIO0_IR) & 0x00100200; /* get config bits */
+ value = in_be32((void*)GPIO0_IR) & 0x00100200; /* get config bits */
/*
* Restore GPIO settings
@@ -137,10 +138,10 @@ int board_early_init_f (void)
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
- out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
- out32(GPIO0_OR, 0); /* pull prg low */
+ out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void*)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void*)GPIO0_OR, 0); /* pull prg low */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@@ -181,15 +182,6 @@ int board_early_init_f (void)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned char *dst;
@@ -205,8 +197,8 @@ int misc_init_r (void)
* FPGA can be gzip compressed (malloc) and booted this late.
*/
- dst = malloc(CFG_FPGA_MAX_SIZE);
- if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+ dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+ if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
printf ("GUNZIP ERROR - must RESET board to recover\n");
do_reset (NULL, 0, 0, NULL);
}
@@ -284,13 +276,11 @@ int misc_init_r (void)
*magic = 0; /* clear pci reconfig magic again */
}
-#if 1 /* test-only */
/*
* Decrease PLB latency timeout and reduce priority of the PCI bridge master
*/
#define PCI0_BRDGOPT1 0x4a
pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
-/* pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f60); */
#define plb0_acr 0x87
/*
@@ -298,14 +288,6 @@ int misc_init_r (void)
*/
mtdcr(plb0_acr, 0x98000000);
-#if 0 /* test-only */
- printf("CCR0=%08x\n", mfspr(ccr0)); /* test-only */
-/* mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00100000); */
- mtspr(ccr0, (mfspr(ccr0) & 0xff8fffff) | 0x00000000);
-#endif
-/* printf("CCR0=%08x\n", mfspr(ccr0)); */ /* test-only */
-#endif
-
free(dst);
return (0);
}
@@ -314,7 +296,6 @@ int misc_init_r (void)
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
char str[64];
@@ -340,14 +321,14 @@ int checkboard (void)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
- out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x40000000);
- out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x40000000);
+ out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
+ out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
udelay(1000); /* wait some time before reading input */
- value = in32(GPIO0_IR) & 0x40000000; /* get config bits */
+ value = in_be32((void*)GPIO0_IR) & 0x40000000; /* get config bits */
if (value) {
puts(", 33 MHz PCI");
} else {
- puts(", 66 Mhz PCI");
+ puts(", 66 MHz PCI");
}
}
@@ -357,37 +338,6 @@ int checkboard (void)
}
/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
-#if 0 /* test-only: all PCI405 version must report 16mb */
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-#else
- return (16*1024*1024);
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
int wpeeprom(int wp)
{
int wp_state = wp;
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-23 05:36:24 +0000