summaryrefslogtreecommitdiff
path: root/board/mucmc52/mucmc52.c
diff options
context:
space:
mode:
Diffstat (limited to 'board/mucmc52/mucmc52.c')
-rw-r--r--board/mucmc52/mucmc52.c98
1 files changed, 49 insertions, 49 deletions
diff --git a/board/mucmc52/mucmc52.c b/board/mucmc52/mucmc52.c
index ae3ca2422..7181bd8a4 100644
--- a/board/mucmc52/mucmc52.c
+++ b/board/mucmc52/mucmc52.c
@@ -37,7 +37,7 @@
#include <asm/processor.h>
#include <asm/io.h>
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -86,7 +86,7 @@ static void sdram_start (int hi_addr)
/*
* ATTENTION: Although partially referenced initdram does NOT make real use
- * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
* is something else than 0x00000000.
*/
@@ -96,7 +96,7 @@ phys_size_t initdram (int board_type)
ulong dramsize2 = 0;
uint svr, pvr;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
ulong test1, test2;
/* setup SDRAM chip selects */
@@ -117,9 +117,9 @@ phys_size_t initdram (int board_type)
/* find RAM size using SDRAM CS0 only */
sdram_start (0);
- test1 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000);
+ test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
sdram_start(1);
- test2 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000);
+ test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
if (test1 > test2) {
sdram_start (0);
dramsize = test1;
@@ -146,10 +146,10 @@ phys_size_t initdram (int board_type)
/* find RAM size using SDRAM CS1 only */
if (!dramsize)
sdram_start (0);
- test2 = test1 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
if (!dramsize) {
sdram_start (1);
- test2 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+ test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
}
if (test1 > test2) {
sdram_start (0);
@@ -171,7 +171,7 @@ phys_size_t initdram (int board_type)
out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
}
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
@@ -189,25 +189,25 @@ phys_size_t initdram (int board_type)
dramsize2 = 0;
}
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
/*
- * On MPC5200B we need to set the special configuration delay in the
- * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
- * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
- *
- * "The SDelay should be written to a value of 0x00000004. It is
- * required to account for changes caused by normal wafer processing
- * parameters."
- */
- svr = get_svr();
- pvr = get_pvr();
- if ((SVR_MJREV(svr) >= 2) &&
- (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
-
- out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
- __asm__ volatile ("sync");
- }
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_SDELAY, 0x04);
+ __asm__ volatile ("sync");
+ }
return dramsize + dramsize2;
}
@@ -239,8 +239,8 @@ struct kbd_data_t {
struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
{
- kbd_data->s1 = in_8 ((volatile uchar*)CFG_STATUS1_BASE);
- kbd_data->s2 = in_8 ((volatile uchar*)CFG_STATUS2_BASE);
+ kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE);
+ kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE);
return kbd_data;
}
@@ -339,14 +339,14 @@ int misc_init_r (void)
free (str);
#endif /* CONFIG_PREBOOT */
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' ');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' ');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' ');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' ');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' ');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' ');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' ');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' ');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' ');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' ');
return 0;
}
@@ -354,27 +354,27 @@ int misc_init_r (void)
int board_early_init_r (void)
{
out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
- out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CFG_FLASH_BASE));
- out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CFG_FLASH_BASE));
+ out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE));
+ out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE));
out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
- STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE));
+ STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
- STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE));
+ STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
return 0;
}
int last_stage_init (void)
{
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5');
- out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2');
-
- return 0;
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5');
+ out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2');
+
+ return 0;
}
#if defined(CONFIG_HW_WATCHDOG)
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-23 03:21:11 +0000