diff options
Diffstat (limited to 'include/asm-m68k/coldfire/flexbus.h')
| -rw-r--r-- | include/asm-m68k/coldfire/flexbus.h | 96 |
1 files changed, 59 insertions, 37 deletions
diff --git a/include/asm-m68k/coldfire/flexbus.h b/include/asm-m68k/coldfire/flexbus.h index 1d902c07f..51cbbd8b2 100644 --- a/include/asm-m68k/coldfire/flexbus.h +++ b/include/asm-m68k/coldfire/flexbus.h @@ -31,33 +31,36 @@ *********************************************************************/ typedef struct fbcs { - u32 csar0; /* Chip-select Address Register */ - u32 csmr0; /* Chip-select Mask Register */ - u32 cscr0; /* Chip-select Control Register */ - u32 csar1; /* Chip-select Address Register */ - u32 csmr1; /* Chip-select Mask Register */ - u32 cscr1; /* Chip-select Control Register */ - u32 csar2; /* Chip-select Address Register */ - u32 csmr2; /* Chip-select Mask Register */ - u32 cscr2; /* Chip-select Control Register */ - u32 csar3; /* Chip-select Address Register */ - u32 csmr3; /* Chip-select Mask Register */ - u32 cscr3; /* Chip-select Control Register */ - u32 csar4; /* Chip-select Address Register */ - u32 csmr4; /* Chip-select Mask Register */ - u32 cscr4; /* Chip-select Control Register */ - u32 csar5; /* Chip-select Address Register */ - u32 csmr5; /* Chip-select Mask Register */ - u32 cscr5; /* Chip-select Control Register */ + u32 csar0; /* Chip-select Address */ + u32 csmr0; /* Chip-select Mask */ + u32 cscr0; /* Chip-select Control */ + u32 csar1; + u32 csmr1; + u32 cscr1; + u32 csar2; + u32 csmr2; + u32 cscr2; + u32 csar3; + u32 csmr3; + u32 cscr3; + u32 csar4; + u32 csmr4; + u32 cscr4; + u32 csar5; + u32 csmr5; + u32 cscr5; + u32 csar6; + u32 csmr6; + u32 cscr6; + u32 csar7; + u32 csmr7; + u32 cscr7; } fbcs_t; -/* Bit definitions and macros for CSAR group */ -#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000) +#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000) -/* Bit definitions and macros for CSMR group */ -#define FBCS_CSMR_V (0x00000001) /* Valid bit */ -#define FBCS_CSMR_WP (0x00000100) /* Write protect */ -#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */ +#define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16) +#define FBCS_CSMR_BAM_MASK (0x0000FFFF) #define FBCS_CSMR_BAM_4G (0xFFFF0000) #define FBCS_CSMR_BAM_2G (0x7FFF0000) #define FBCS_CSMR_BAM_1G (0x3FFF0000) @@ -78,21 +81,40 @@ typedef struct fbcs { #define FBCS_CSMR_BAM_128K (0x00010000) #define FBCS_CSMR_BAM_64K (0x00000000) -/* Bit definitions and macros for CSCR group */ -#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */ -#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */ -#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */ -#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */ -#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */ -#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */ -#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */ -#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */ -#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */ -#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */ -#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */ +#ifdef CONFIG_M5249 +#define FBCS_CSMR_WP (0x00000080) +#define FBCS_CSMR_AM (0x00000040) +#define FBCS_CSMR_CI (0x00000020) +#define FBCS_CSMR_SC (0x00000010) +#define FBCS_CSMR_SD (0x00000008) +#define FBCS_CSMR_UC (0x00000004) +#define FBCS_CSMR_UD (0x00000002) +#else +#define FBCS_CSMR_WP (0x00000100) +#endif +#define FBCS_CSMR_V (0x00000001) /* Valid bit */ + +#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26) +#define FBCS_CSCR_SWS_MASK (0x03FFFFFF) +#define FBCS_CSCR_SWSEN (0x00800000) +#define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20) +#define FBCS_CSCR_ASET_MASK (0xFFCFFFFF) +#define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18) +#define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF) +#define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16) +#define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF) +#define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10) +#define FBCS_CSCR_WS_MASK (0xFFFF03FF) +#define FBCS_CSCR_SBM (0x00000200) +#define FBCS_CSCR_AA (0x00000100) +#define FBCS_CSCR_PS(x) (((x) & 0x03) << 6) +#define FBCS_CSCR_PS_MASK (0xFFFFFF3F) +#define FBCS_CSCR_BEM (0x00000020) +#define FBCS_CSCR_BSTR (0x00000010) +#define FBCS_CSCR_BSTW (0x00000008) -#define FBCS_CSCR_PS_8 (0x00000040) #define FBCS_CSCR_PS_16 (0x00000080) +#define FBCS_CSCR_PS_8 (0x00000040) #define FBCS_CSCR_PS_32 (0x00000000) #endif /* __FLEXBUS_H */ |