diff options
author | Katarzyna Dec <katarzyna.dec@intel.com> | 2018-10-03 15:48:40 +0200 |
---|---|---|
committer | Arkadiusz Hiler <arkadiusz.hiler@intel.com> | 2018-10-04 10:34:20 +0300 |
commit | bba38422e7f903094562f1b78cc3579683c0a667 (patch) | |
tree | 7fd83bb1e48a22c69a19d8c170e841f9d786bd62 /lib/i915/shaders/gpgpu | |
parent | 1bc6ea2488c8f1c460565f9795938e09f613d8d4 (diff) |
lib/i915: Move shaders directory
In shaders/ directory we got Intel specific information. As igt
is a project for more vendors, let's move this directory to
lib/i915.
v2: Changed shaders directory path in library files comments.
Signed-off-by: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Kalamarz Lukasz <lukasz.kalamarz@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'lib/i915/shaders/gpgpu')
-rw-r--r-- | lib/i915/shaders/gpgpu/gpgpu_fill.gxa | 39 | ||||
-rw-r--r-- | lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm | 10 | ||||
-rw-r--r-- | lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm | 10 |
3 files changed, 59 insertions, 0 deletions
diff --git a/lib/i915/shaders/gpgpu/gpgpu_fill.gxa b/lib/i915/shaders/gpgpu/gpgpu_fill.gxa new file mode 100644 index 00000000..34d473c1 --- /dev/null +++ b/lib/i915/shaders/gpgpu/gpgpu_fill.gxa @@ -0,0 +1,39 @@ +/* + * Registers + * g0 -- header + * g1 -- constant + * g2 -- calculate X/Y offset + * g4-g12 payload for write message + */ +define(`ORIG', `g2.0<2,2,1>UD') +define(`ORIG_X', `g2.0<1>UD') +define(`ORIG_Y', `g2.4<1>UD') +define(`COLOR', `g1.0') +define(`COLORUB', `COLOR<0,1,0>UB') +define(`COLORUD', `COLOR<0,1,0>UD') +define(`X', `g0.4<0,1,0>UD') +define(`Y', `g0.24<0,1,0>UD') + +mov(4) COLOR<1>UB COLORUB {align1}; + +/* WRITE */ +/* count thread group ID for X/Y offset */ +mul(1) ORIG_X X 0x10UD {align1}; +mov(1) ORIG_Y Y {align1}; +mov(8) g4.0<1>UD g0.0<8,8,1>UD {align1}; +mov(2) g4.0<1>UD ORIG {align1}; +/* Normal mode: for block height 1 row and block width 16 bytes */ +mov(1) g4.8<1>UD 0x0000000fUD {align1}; + +mov(16) g5.0<1>UD COLORUD {align1 compr}; + +/* + * write(0, 0, 10, 12) + * 10: media_block_write + * 12: data cache data port 1 + */ +send(16) 4 acc0<1>UW null write(0, 0, 10, 12) mlen 3 rlen 0 {align1}; + +/* EOT */ +mov(8) g112.0<1>UD g0.0<8,8,1>UD {align1}; +send(16) 112 null<1>UW null thread_spawner(0, 0, 1) mlen 1 rlen 0 {align1 EOT}; diff --git a/lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm b/lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm new file mode 100644 index 00000000..448e0256 --- /dev/null +++ b/lib/i915/shaders/gpgpu/gpgpu_fill_gen8.asm @@ -0,0 +1,10 @@ + mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub + mul (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x10:ud + mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud + mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud + mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud + mov (1|M0) r4.2<1>:ud 0xF:ud + mov (16|M0) (eq)f0.0 r5.0<1>:ud r1.0<0;1,0>:ud + send (16|M0) acc0.0:uw r4:d 0xC 0x060A8000 // DP_DC1 wr:3h, rd:0, fc: 0x28000 + mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud + send (16|M0) null:uw r112:d 0x27 0x02000010 {EOT} // SPAWNER wr:1, rd:0, fc: 0x10 diff --git a/lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm b/lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm new file mode 100644 index 00000000..6f948935 --- /dev/null +++ b/lib/i915/shaders/gpgpu/gpgpu_fill_gen9.asm @@ -0,0 +1,10 @@ + mov (4|M0) r1.0<1>:ub r1.0<0;1,0>:ub + mul (1|M0) r2.0<1>:ud r0.1<0;1,0>:ud 0x10:ud + mov (1|M0) r2.1<1>:ud r0.6<0;1,0>:ud + mov (8|M0) r4.0<1>:ud r0.0<8;8,1>:ud + mov (2|M0) r4.0<1>:ud r2.0<2;2,1>:ud + mov (1|M0) r4.2<1>:ud 0xF:ud + mov (16|M0) r5.0<1>:ud r1.0<0;1,0>:ud + send (16|M0) acc0.0:uw r4:d 0xC 0x060A8000 // DP_DC1 wr:3h, rd:0, fc: 0x28000 + mov (8|M0) r112.0<1>:ud r0.0<8;8,1>:ud + send (16|M0) null:uw r112:d 0x27 0x02000010 {EOT} // SPAWNER wr:1, rd:0, fc: 0x10 |