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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-11-29 11:06:37 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2018-12-04 10:29:57 +0100 |
| commit | 515b2915ee08060ad4f6a3b3de38c5c2c5258e8b (patch) | |
| tree | 98b21be03fa059bc6660aae2cea02752f2ce9ca7 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 7cf3a216a2b3a672cad3e498c186c9333bdff90a (diff) | |
clk: renesas: r8a77995: Correct parent clock of DU
According to the R-Car Gen3 Hardware Manual Rev 1.00, the parent clock
of the DU module clocks on R-Car D3 is S1D1.
Fixes: d71e851d82c6cfe5 ("clk: renesas: cpg-mssr: Add R8A77995 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions