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| author | Gayatri Kammela <gayatri.kammela@intel.com> | 2021-04-16 20:12:51 -0700 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2021-04-19 10:44:28 +0200 |
| commit | 43ef6c226a60b1c52890791af73f7015f68a315a (patch) | |
| tree | e071fd2764dd06b8e488ccd519eaa53dc3552708 /tools/perf/scripts/python/exported-sql-viewer.py | |
| parent | 8074a79fad2e34fce11ea2b2c515b984fc6b2a08 (diff) | |
platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information
and supports a few additional registers. Hence add the LTR registers
specific to Tiger Lake to the cnp_ltr_show_map[].
Also adjust the number of LTR IPs for Tiger Lake to the correct amount.
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Link: https://lore.kernel.org/r/20210417031252.3020837-9-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'tools/perf/scripts/python/exported-sql-viewer.py')
0 files changed, 0 insertions, 0 deletions