diff options
Diffstat (limited to 'drivers/gpu')
46 files changed, 957 insertions, 894 deletions
diff --git a/drivers/gpu/pvr/bridged_pvr_bridge.c b/drivers/gpu/pvr/bridged_pvr_bridge.c index b292d96b582..f1e606c87bc 100644 --- a/drivers/gpu/pvr/bridged_pvr_bridge.c +++ b/drivers/gpu/pvr/bridged_pvr_bridge.c @@ -822,6 +822,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID, NEW_HANDLE_BATCH_OR_ERROR(psMapDevMemOUT->eError, psPerProc, 2) + psMapDevMemOUT->eError = PVRSRVLookupHandle(KERNEL_HANDLE_BASE, (IMG_VOID**)&psSrcKernelMemInfo, psMapDevMemIN->hKernelMemInfo, @@ -831,6 +832,7 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID, return 0; } + psMapDevMemOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, &hDstDevMemHeap, psMapDevMemIN->hDstDevMemHeap, @@ -839,11 +841,20 @@ PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID, { return 0; } + if (psSrcKernelMemInfo->sShareMemWorkaround.bInUse) { PVR_DPF((PVR_DBG_MESSAGE, "using the mem wrap workaround.")); + + + + + + + + psMapDevMemOUT->eError = BM_XProcWorkaroundSetShareIndex(psSrcKernelMemInfo->sShareMemWorkaround.ui32ShareIndex); if(psMapDevMemOUT->eError != PVRSRV_OK) { @@ -3833,11 +3844,13 @@ static PVRSRV_ERROR DoModifyCompleteSyncOps(MODIFY_SYNC_OP_INFO *psModSyncOpInfo static PVRSRV_ERROR ModifyCompleteSyncOpsCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { MODIFY_SYNC_OP_INFO *psModSyncOpInfo; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); if (!pvParam) { @@ -3969,7 +3982,7 @@ PVRSRVDestroySyncInfoModObjBW(IMG_UINT32 return 0; } - psDestroySyncInfoModObjOUT->eError = ResManFreeResByPtr(psModSyncOpInfo->hResItem); + psDestroySyncInfoModObjOUT->eError = ResManFreeResByPtr(psModSyncOpInfo->hResItem, CLEANUP_WITH_POLL); if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: ResManFreeResByPtr failed")); @@ -4274,12 +4287,14 @@ PVRSRVSyncOpsFlushToDeltaBW(IMG_UINT32 u static PVRSRV_ERROR FreeSyncInfoCallback(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; PVRSRV_ERROR eError; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)pvParam; @@ -4396,7 +4411,7 @@ PVRSRVFreeSyncInfoBW(IMG_UINT32 ui32Bri return 0; } - eError = ResManFreeResByPtr(psSyncInfo->hResItem); + eError = ResManFreeResByPtr(psSyncInfo->hResItem, CLEANUP_WITH_POLL); if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: ResManFreeResByPtr failed")); diff --git a/drivers/gpu/pvr/buffer_manager.c b/drivers/gpu/pvr/buffer_manager.c index a8240585fb3..7b3cd7a1545 100644 --- a/drivers/gpu/pvr/buffer_manager.c +++ b/drivers/gpu/pvr/buffer_manager.c @@ -526,6 +526,7 @@ static IMG_VOID FreeBuf (BM_BUF *pBuf, IMG_UINT32 ui32Flags, IMG_BOOL bFromAllocator) { BM_MAPPING *pMapping; + PVRSRV_DEVICE_NODE *psDeviceNode; PVR_DPF ((PVR_DBG_MESSAGE, "FreeBuf: pBuf=0x%x: DevVAddr=%08X CpuVAddr=0x%x CpuPAddr=%08X", @@ -535,6 +536,12 @@ FreeBuf (BM_BUF *pBuf, IMG_UINT32 ui32Flags, IMG_BOOL bFromAllocator) pMapping = pBuf->pMapping; + psDeviceNode = pMapping->pBMHeap->pBMContext->psDeviceNode; + if (psDeviceNode->pfnCacheInvalidate) + { + psDeviceNode->pfnCacheInvalidate(psDeviceNode); + } + if(ui32Flags & PVRSRV_MEM_USER_SUPPLIED_DEVVADDR) { @@ -695,7 +702,7 @@ BM_DestroyContext(IMG_HANDLE hBMContext, else { - eError = ResManFreeResByPtr(pBMContext->hResItem); + eError = ResManFreeResByPtr(pBMContext->hResItem, CLEANUP_WITH_POLL); if(eError != PVRSRV_OK) { PVR_DPF ((PVR_DBG_ERROR, "BM_DestroyContext: ResManFreeResByPtr failed %d",eError)); @@ -745,13 +752,15 @@ static PVRSRV_ERROR BM_DestroyContextCallBack_AnyVaCb(BM_HEAP *psBMHeap, va_list } -static PVRSRV_ERROR BM_DestroyContextCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) +static PVRSRV_ERROR BM_DestroyContextCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { BM_CONTEXT *pBMContext = pvParam; PVRSRV_DEVICE_NODE *psDeviceNode; PVRSRV_ERROR eError; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); @@ -969,7 +978,7 @@ BM_CreateContext(PVRSRV_DEVICE_NODE *psDeviceNode, return (IMG_HANDLE)pBMContext; cleanup: - (IMG_VOID)BM_DestroyContextCallBack(pBMContext, 0); + (IMG_VOID)BM_DestroyContextCallBack(pBMContext, 0, CLEANUP_WITH_POLL); return IMG_NULL; } @@ -1723,7 +1732,9 @@ DevMemoryFree (BM_MAPPING *pMapping) psDeviceNode->pfnMMUFree (pMapping->pBMHeap->pMMUHeap, pMapping->DevVAddr, IMG_CAST_TO_DEVVADDR_UINT(pMapping->uSize)); } +#ifndef XPROC_WORKAROUND_NUM_SHAREABLES #define XPROC_WORKAROUND_NUM_SHAREABLES 200 +#endif #define XPROC_WORKAROUND_BAD_SHAREINDEX 0773407734 diff --git a/drivers/gpu/pvr/device.h b/drivers/gpu/pvr/device.h index 86f37c6cd4e..9df2c734bc6 100644 --- a/drivers/gpu/pvr/device.h +++ b/drivers/gpu/pvr/device.h @@ -246,7 +246,9 @@ typedef struct _PVRSRV_DEVICE_NODE_ IMG_VOID (*pfnDeviceCommandComplete)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode); IMG_BOOL bReProcessDeviceCommandComplete; - + + IMG_VOID (*pfnCacheInvalidate)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode); + DEVICE_MEMORY_INFO sDevMemoryInfo; diff --git a/drivers/gpu/pvr/deviceclass.c b/drivers/gpu/pvr/deviceclass.c index 0e4b51a57e0..7b565dd8168 100644 --- a/drivers/gpu/pvr/deviceclass.c +++ b/drivers/gpu/pvr/deviceclass.c @@ -258,7 +258,7 @@ PVRSRV_ERROR PVRSRVRegisterDCDeviceKM (PVRSRV_DC_SRV2DISP_KMJTABLE *psFuncTable, *psDCInfo->psFuncTable = *psFuncTable; - if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP, + if(OSAllocMem( PVRSRV_OS_NON_PAGEABLE_HEAP, sizeof(PVRSRV_DEVICE_NODE), (IMG_VOID **)&psDeviceNode, IMG_NULL, "Device Node") != PVRSRV_OK) @@ -420,7 +420,7 @@ PVRSRV_ERROR PVRSRVRegisterBCDeviceKM (PVRSRV_BC_SRV2BUFFER_KMJTABLE *psFuncTabl *psBCInfo->psFuncTable = *psFuncTable; - if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP, + if(OSAllocMem( PVRSRV_OS_NON_PAGEABLE_HEAP, sizeof(PVRSRV_DEVICE_NODE), (IMG_VOID **)&psDeviceNode, IMG_NULL, "Device Node") != PVRSRV_OK) @@ -540,19 +540,21 @@ PVRSRV_ERROR PVRSRVCloseDCDeviceKM (IMG_HANDLE hDeviceKM, psDCPerContextInfo = (PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *)hDeviceKM; - eError = ResManFreeResByPtr(psDCPerContextInfo->hResItem); + eError = ResManFreeResByPtr(psDCPerContextInfo->hResItem, CLEANUP_WITH_POLL); return eError; } -static PVRSRV_ERROR CloseDCDeviceCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) +static PVRSRV_ERROR CloseDCDeviceCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *psDCPerContextInfo; PVRSRV_DISPLAYCLASS_INFO *psDCInfo; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); psDCPerContextInfo = (PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *)pvParam; psDCInfo = psDCPerContextInfo->psDCInfo; @@ -812,7 +814,7 @@ PVRSRV_ERROR PVRSRVDestroyDCSwapChainKM(IMG_HANDLE hSwapChainRef) psSwapChainRef = hSwapChainRef; - eError = ResManFreeResByPtr(psSwapChainRef->hResItem); + eError = ResManFreeResByPtr(psSwapChainRef->hResItem, CLEANUP_WITH_POLL); return eError; } @@ -880,13 +882,16 @@ static PVRSRV_ERROR DestroyDCSwapChain(PVRSRV_DC_SWAPCHAIN *psSwapChain) } -static PVRSRV_ERROR DestroyDCSwapChainRefCallBack(IMG_PVOID pvParam, IMG_UINT32 ui32Param) +static PVRSRV_ERROR DestroyDCSwapChainRefCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_DC_SWAPCHAIN_REF *psSwapChainRef = (PVRSRV_DC_SWAPCHAIN_REF *) pvParam; PVRSRV_ERROR eError = PVRSRV_OK; IMG_UINT32 i; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); for (i = 0; i < psSwapChainRef->psSwapChain->ui32BufferCount; i++) { @@ -1705,20 +1710,22 @@ PVRSRV_ERROR PVRSRVCloseBCDeviceKM (IMG_HANDLE hDeviceKM, psBCPerContextInfo = (PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *)hDeviceKM; - eError = ResManFreeResByPtr(psBCPerContextInfo->hResItem); + eError = ResManFreeResByPtr(psBCPerContextInfo->hResItem, CLEANUP_WITH_POLL); return eError; } -static PVRSRV_ERROR CloseBCDeviceCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) +static PVRSRV_ERROR CloseBCDeviceCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *psBCPerContextInfo; PVRSRV_BUFFERCLASS_INFO *psBCInfo; IMG_UINT32 i; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); psBCPerContextInfo = (PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *)pvParam; diff --git a/drivers/gpu/pvr/devicemem.c b/drivers/gpu/pvr/devicemem.c index 3016736c5c1..adf8e774880 100644 --- a/drivers/gpu/pvr/devicemem.c +++ b/drivers/gpu/pvr/devicemem.c @@ -662,11 +662,14 @@ static PVRSRV_ERROR FreeMemCallBackCommon(PVRSRV_KERNEL_MEM_INFO *psMemInfo, return eError; } -static PVRSRV_ERROR FreeDeviceMemCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) +static PVRSRV_ERROR FreeDeviceMemCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_KERNEL_MEM_INFO *psMemInfo = (PVRSRV_KERNEL_MEM_INFO *)pvParam; + PVR_UNREFERENCED_PARAMETER(bDummy); + return FreeMemCallBackCommon(psMemInfo, ui32Param, IMG_TRUE); } @@ -686,12 +689,12 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeDeviceMemKM(IMG_HANDLE hDevCookie, if (psMemInfo->sMemBlk.hResItem != IMG_NULL) { - eError = ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem); + eError = ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL); } else { - eError = FreeDeviceMemCallBack(psMemInfo, 0); + eError = FreeDeviceMemCallBack(psMemInfo, 0, CLEANUP_WITH_POLL); } return eError; @@ -849,15 +852,18 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVUnwrapExtMemoryKM (PVRSRV_KERNEL_MEM_INFO *psMem return PVRSRV_ERROR_INVALID_PARAMS; } - return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem); + return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL); } -static PVRSRV_ERROR UnwrapExtMemoryCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) +static PVRSRV_ERROR UnwrapExtMemoryCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_KERNEL_MEM_INFO *psMemInfo = (PVRSRV_KERNEL_MEM_INFO *)pvParam; + PVR_UNREFERENCED_PARAMETER(bDummy); + return FreeMemCallBackCommon(psMemInfo, ui32Param, IMG_TRUE); } @@ -1101,17 +1107,19 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapDeviceMemoryKM (PVRSRV_KERNEL_MEM_INFO *psM return PVRSRV_ERROR_INVALID_PARAMS; } - return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem); + return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL); } -static PVRSRV_ERROR UnmapDeviceMemoryCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) +static PVRSRV_ERROR UnmapDeviceMemoryCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_ERROR eError; RESMAN_MAP_DEVICE_MEM_DATA *psMapData = pvParam; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); if(psMapData->psMemInfo->sMemBlk.psIntSysPAddr) { @@ -1350,17 +1358,19 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapDeviceClassMemoryKM(PVRSRV_KERNEL_MEM_INFO return PVRSRV_ERROR_INVALID_PARAMS; } - return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem); + return ResManFreeResByPtr(psMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL); } -static PVRSRV_ERROR UnmapDeviceClassMemoryCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) +static PVRSRV_ERROR UnmapDeviceClassMemoryCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_DC_MAPINFO *psDCMapInfo = pvParam; PVRSRV_KERNEL_MEM_INFO *psMemInfo; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); psMemInfo = psDCMapInfo->psMemInfo; @@ -1378,9 +1388,6 @@ static PVRSRV_ERROR UnmapDeviceClassMemoryCallBack(IMG_PVOID pvParam, #endif (psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount)--; - PVR_TRACE(("decrementing (0x%p) psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount... == %d", - psDCMapInfo->psDeviceClassBuffer, - psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount)); OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_DC_MAPINFO), psDCMapInfo, IMG_NULL); @@ -1588,10 +1595,6 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA * &UnmapDeviceClassMemoryCallBack); (psDeviceClassBuffer->ui32MemMapRefCount)++; - PVR_TRACE(("incrementing (0x%p) psDeviceClassBuffer->ui32MemMapRefCount... == %d", - psDeviceClassBuffer, - psDeviceClassBuffer->ui32MemMapRefCount)); - psMemInfo->ui32RefCount++; psMemInfo->memType = PVRSRV_MEMTYPE_DEVICECLASS; diff --git a/drivers/gpu/pvr/event.c b/drivers/gpu/pvr/event.c index e8797c4ecb9..888871b3a92 100644 --- a/drivers/gpu/pvr/event.c +++ b/drivers/gpu/pvr/event.c @@ -140,7 +140,7 @@ PVRSRV_ERROR LinuxEventObjectDelete(IMG_HANDLE hOSEventObjectList, IMG_HANDLE hO #if defined(DEBUG) PVR_DPF((PVR_DBG_MESSAGE, "LinuxEventObjectListDelete: Event object waits: %u", psLinuxEventObject->ui32Stats)); #endif - if(ResManFreeResByPtr(psLinuxEventObject->hResItem) != PVRSRV_OK) + if(ResManFreeResByPtr(psLinuxEventObject->hResItem, CLEANUP_WITH_POLL) != PVRSRV_OK) { return PVRSRV_ERROR_UNABLE_TO_DESTROY_EVENT; } @@ -152,13 +152,14 @@ PVRSRV_ERROR LinuxEventObjectDelete(IMG_HANDLE hOSEventObjectList, IMG_HANDLE hO } -static PVRSRV_ERROR LinuxEventObjectDeleteCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param) +static PVRSRV_ERROR LinuxEventObjectDeleteCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bForceCleanup) { PVRSRV_LINUX_EVENT_OBJECT *psLinuxEventObject = pvParam; PVRSRV_LINUX_EVENT_OBJECT_LIST *psLinuxEventObjectList = psLinuxEventObject->psLinuxEventObjectList; unsigned long ulLockFlags; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bForceCleanup); write_lock_irqsave(&psLinuxEventObjectList->sLock, ulLockFlags); list_del(&psLinuxEventObject->sList); diff --git a/drivers/gpu/pvr/img_defs.h b/drivers/gpu/pvr/img_defs.h index 3ef43aad611..8ca49d2d076 100644 --- a/drivers/gpu/pvr/img_defs.h +++ b/drivers/gpu/pvr/img_defs.h @@ -109,6 +109,9 @@ typedef char TCHAR, *PTCHAR, *PTSTR; #define IMG_FORMAT_PRINTF(x,y) #endif +#define CLEANUP_WITH_POLL IMG_FALSE +#define FORCE_CLEANUP IMG_TRUE + #if defined (_WIN64) #define IMG_UNDEF (~0ULL) #else diff --git a/drivers/gpu/pvr/img_types.h b/drivers/gpu/pvr/img_types.h index 4401f4dd92c..3800afb5644 100644 --- a/drivers/gpu/pvr/img_types.h +++ b/drivers/gpu/pvr/img_types.h @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -104,6 +104,13 @@ typedef void** IMG_HVOID, * IMG_PHVOID; typedef IMG_UINT32 IMG_SID; typedef IMG_UINT32 IMG_EVENTSID; + +#if defined(SUPPORT_SID_INTERFACE) + typedef IMG_SID IMG_S_HANDLE; +#else + typedef IMG_HANDLE IMG_S_HANDLE; +#endif + typedef IMG_PVOID IMG_CPU_VIRTADDR; typedef struct _IMG_DEV_VIRTADDR diff --git a/drivers/gpu/pvr/mem.c b/drivers/gpu/pvr/mem.c index f71644e572f..5b5d1ac541a 100644 --- a/drivers/gpu/pvr/mem.c +++ b/drivers/gpu/pvr/mem.c @@ -29,12 +29,14 @@ static PVRSRV_ERROR -FreeSharedSysMemCallBack(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) +FreeSharedSysMemCallBack(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bDummy) { PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo = pvParam; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); OSFreePages(psKernelMemInfo->ui32Flags, psKernelMemInfo->uAllocSize, @@ -111,11 +113,11 @@ PVRSRVFreeSharedSysMemoryKM(PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo) if(psKernelMemInfo->sMemBlk.hResItem) { - eError = ResManFreeResByPtr(psKernelMemInfo->sMemBlk.hResItem); + eError = ResManFreeResByPtr(psKernelMemInfo->sMemBlk.hResItem, CLEANUP_WITH_POLL); } else { - eError = FreeSharedSysMemCallBack(psKernelMemInfo, 0); + eError = FreeSharedSysMemCallBack(psKernelMemInfo, 0, CLEANUP_WITH_POLL); } return eError; diff --git a/drivers/gpu/pvr/module.c b/drivers/gpu/pvr/module.c index cb05ea76cbf..f689f363d4c 100644 --- a/drivers/gpu/pvr/module.c +++ b/drivers/gpu/pvr/module.c @@ -28,7 +28,9 @@ #include <linux/config.h> #endif -#if !defined(SUPPORT_DRI_DRM) +#if defined(SUPPORT_DRI_DRM) +#define PVR_MOD_STATIC +#else #if defined(LDM_PLATFORM) #define PVR_LDM_PLATFORM_MODULE @@ -39,6 +41,13 @@ #define PVR_LDM_MODULE #endif #endif +#define PVR_MOD_STATIC static +#endif + +#if defined(PVR_LDM_PLATFORM_PRE_REGISTERED) +#if !defined(NO_HARDWARE) +#define PVR_USE_PRE_REGISTERED_PLATFORM_DEV +#endif #endif #include <linux/init.h> @@ -152,7 +161,6 @@ static IMG_UINT32 gPVRPowerLevel; #define LDM_DEV struct pci_dev #define LDM_DRV struct pci_driver #endif - #if defined(PVR_LDM_PLATFORM_MODULE) static int PVRSRVDriverRemove(LDM_DEV *device); static int PVRSRVDriverProbe(LDM_DEV *device); @@ -167,16 +175,23 @@ static int PVRSRVDriverResume(LDM_DEV *device); #if defined(PVR_LDM_PCI_MODULE) struct pci_device_id powervr_id_table[] __devinitdata = { - { PCI_DEVICE(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV_DEVICE_ID) }, + {PCI_DEVICE(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV_DEVICE_ID)}, #if defined (SYS_SGX_DEV1_DEVICE_ID) - { PCI_DEVICE(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV1_DEVICE_ID) }, + {PCI_DEVICE(SYS_SGX_DEV_VENDOR_ID, SYS_SGX_DEV1_DEVICE_ID)}, #endif - { 0 } + {0} }; MODULE_DEVICE_TABLE(pci, powervr_id_table); #endif +#if defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV) +static struct platform_device_id powervr_id_table[] __devinitdata = { + {SYS_SGX_DEV_NAME, 0}, + {} +}; +#endif + static LDM_DRV powervr_driver = { #if defined(PVR_LDM_PLATFORM_MODULE) .driver = { @@ -185,6 +200,8 @@ static LDM_DRV powervr_driver = { #endif #if defined(PVR_LDM_PCI_MODULE) .name = DRVNAME, +#endif +#if defined(PVR_LDM_PCI_MODULE) || defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV) .id_table = powervr_id_table, #endif .probe = PVRSRVDriverProbe, @@ -201,9 +218,9 @@ static LDM_DRV powervr_driver = { LDM_DEV *gpsPVRLDMDev; -#if defined(MODULE) && defined(PVR_LDM_PLATFORM_MODULE) - -static IMG_VOID PVRSRVDeviceRelease(struct device unref__ *pDevice) +#if defined(MODULE) && defined(PVR_LDM_PLATFORM_MODULE) && \ + !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV) +static void PVRSRVDeviceRelease(struct device unref__ *pDevice) { } @@ -214,8 +231,7 @@ static struct platform_device powervr_device = { .release = PVRSRVDeviceRelease } }; - -#endif +#endif #if defined(PVR_LDM_PLATFORM_MODULE) static int PVRSRVDriverProbe(LDM_DEV *pDevice) @@ -273,7 +289,7 @@ static void __devexit PVRSRVDriverRemove(LDM_DEV *pDevice) } } #endif - (IMG_VOID)SysDeinitialise(psSysData); + (void) SysDeinitialise(psSysData); gpsPVRLDMDev = IMG_NULL; @@ -291,23 +307,25 @@ static void __devexit PVRSRVDriverRemove(LDM_DEV *pDevice) return; #endif } +#endif -static IMG_VOID PVRSRVDriverShutdown(LDM_DEV *pDevice) +#if defined(PVR_LDM_MODULE) || defined(PVR_DRI_DRM_PLATFORM_DEV) +PVR_MOD_STATIC void PVRSRVDriverShutdown(LDM_DEV *pDevice) { PVR_TRACE(("PVRSRVDriverShutdown(pDevice=%p)", pDevice)); - (IMG_VOID) PVRSRVSetPowerStateKM(PVRSRV_SYS_POWER_STATE_D3); + (void) PVRSRVSetPowerStateKM(PVRSRV_SYS_POWER_STATE_D3); } #endif #if defined(PVR_LDM_MODULE) || defined(SUPPORT_DRI_DRM) -#if defined(SUPPORT_DRI_DRM) +#if defined(SUPPORT_DRI_DRM) && !defined(PVR_DRI_DRM_PLATFORM_DEV) int PVRSRVDriverSuspend(struct drm_device *pDevice, pm_message_t state) #else -static int PVRSRVDriverSuspend(LDM_DEV *pDevice, pm_message_t state) +PVR_MOD_STATIC int PVRSRVDriverSuspend(LDM_DEV *pDevice, pm_message_t state) #endif { #if !(defined(DEBUG) && defined(PVR_MANUAL_POWER_CONTROL) && !defined(SUPPORT_DRI_DRM)) @@ -322,10 +340,10 @@ static int PVRSRVDriverSuspend(LDM_DEV *pDevice, pm_message_t state) } -#if defined(SUPPORT_DRI_DRM) +#if defined(SUPPORT_DRI_DRM) && !defined(PVR_DRI_DRM_PLATFORM_DEV) int PVRSRVDriverResume(struct drm_device *pDevice) #else -static int PVRSRVDriverResume(LDM_DEV *pDevice) +PVR_MOD_STATIC int PVRSRVDriverResume(LDM_DEV *pDevice) #endif { #if !(defined(DEBUG) && defined(PVR_MANUAL_POWER_CONTROL) && !defined(SUPPORT_DRI_DRM)) @@ -492,9 +510,9 @@ static int PVRSRVRelease(struct inode unref__ * pInode, struct file *pFile) #if defined(SUPPORT_DRI_DRM) -int PVRCore_Init(IMG_VOID) +int PVRCore_Init(void) #else -static int __init PVRCore_Init(IMG_VOID) +static int __init PVRCore_Init(void) #endif { int error; @@ -546,7 +564,7 @@ static int __init PVRCore_Init(IMG_VOID) goto init_failed; } -#if defined(MODULE) +#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV) if ((error = platform_device_register(&powervr_device)) != 0) { platform_driver_unregister(&powervr_driver); @@ -638,7 +656,7 @@ sys_deinit: #endif #if defined (PVR_LDM_PLATFORM_MODULE) -#if defined (MODULE) +#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV) platform_device_unregister(&powervr_device); #endif platform_driver_unregister(&powervr_driver); @@ -652,7 +670,7 @@ sys_deinit: psSysData = SysAcquireDataNoCheck(); if (psSysData != IMG_NULL) { - (IMG_VOID)SysDeinitialise(psSysData); + (void) SysDeinitialise(psSysData); } } #endif @@ -674,11 +692,14 @@ void PVRCore_Cleanup(void) static void __exit PVRCore_Cleanup(void) #endif { +#if !defined(PVR_LDM_MODULE) SYS_DATA *psSysData; - +#endif PVR_TRACE(("PVRCore_Cleanup")); +#if !defined(PVR_LDM_MODULE) SysAcquireData(&psSysData); +#endif #if defined(PVR_LDM_MODULE) device_destroy(psPvrClass, MKDEV(AssignedMajorNumber, 0)); @@ -707,7 +728,7 @@ static void __exit PVRCore_Cleanup(void) #endif #if defined (PVR_LDM_PLATFORM_MODULE) -#if defined (MODULE) +#if defined(MODULE) && !defined(PVR_USE_PRE_REGISTERED_PLATFORM_DEV) platform_device_unregister(&powervr_device); #endif platform_driver_unregister(&powervr_driver); @@ -741,6 +762,6 @@ static void __exit PVRCore_Cleanup(void) } #if !defined(SUPPORT_DRI_DRM) -late_initcall(PVRCore_Init); +module_init(PVRCore_Init); module_exit(PVRCore_Cleanup); #endif diff --git a/drivers/gpu/pvr/omap4/sysconfig.c b/drivers/gpu/pvr/omap4/sysconfig.c index f08bf8e13fc..5c82be77d46 100644 --- a/drivers/gpu/pvr/omap4/sysconfig.c +++ b/drivers/gpu/pvr/omap4/sysconfig.c @@ -24,28 +24,18 @@ * ******************************************************************************/ +#include "sysconfig.h" #include "services_headers.h" #include "kerneldisplay.h" #include "oemfuncs.h" #include "sgxinfo.h" #include "sgxinfokm.h" #include "syslocal.h" -#include "sysconfig.h" - -#include <linux/platform_device.h> -#include <plat/omap_device.h> -#include <plat/omap-pm.h> #include "ocpdefs.h" -#if !defined(NO_HARDWARE) && \ - defined(SYS_USING_INTERRUPTS) && \ - defined(SGX540) -#define SGX_OCP_REGS_ENABLED -#endif - -#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) -extern struct platform_device *gpsPVRLDMDev; +#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) +#include <plat/omap_device.h> #endif SYS_DATA* gpsSysData = (SYS_DATA*)IMG_NULL; @@ -60,10 +50,14 @@ static PVRSRV_DEVICE_NODE *gpsSGXDevNode; #define DEVICE_SGX_INTERRUPT (1 << 0) -#if defined(NO_HARDWARE) +#if defined(NO_HARDWARE) || defined(SGX_OCP_REGS_ENABLED) static IMG_CPU_VIRTADDR gsSGXRegsCPUVAddr; #endif +#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) +extern struct platform_device *gpsPVRLDMDev; +#endif + IMG_UINT32 PVRSRV_BridgeDispatchKM(IMG_UINT32 Ioctl, IMG_BYTE *pInBuf, IMG_UINT32 InBufLen, @@ -73,25 +67,19 @@ IMG_UINT32 PVRSRV_BridgeDispatchKM(IMG_UINT32 Ioctl, #if defined(SGX_OCP_REGS_ENABLED) -#define SYS_OMAP4430_OCP_REGS_SYS_PHYS_BASE (SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE + EUR_CR_OCP_REVISION) -#define SYS_OMAP4430_OCP_REGS_SIZE 0x110 - static IMG_CPU_VIRTADDR gpvOCPRegsLinAddr; static PVRSRV_ERROR EnableSGXClocksWrap(SYS_DATA *psSysData) { PVRSRV_ERROR eError = EnableSGXClocks(psSysData); +#if !defined(SGX_OCP_NO_INT_BYPASS) if(eError == PVRSRV_OK) { - OSWriteHWReg(gpvOCPRegsLinAddr, - EUR_CR_OCP_SYSCONFIG - EUR_CR_OCP_REVISION, - 0x14); - OSWriteHWReg(gpvOCPRegsLinAddr, - EUR_CR_OCP_DEBUG_CONFIG - EUR_CR_OCP_REVISION, - EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_MASK); + OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_SYSCONFIG, 0x14); + OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_DEBUG_CONFIG, EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_MASK); } - +#endif return eError; } @@ -112,7 +100,11 @@ static INLINE PVRSRV_ERROR EnableSystemClocksWrap(SYS_DATA *psSysData) if(eError == PVRSRV_OK) { - EnableSGXClocksWrap(psSysData); + eError = EnableSGXClocksWrap(psSysData); + if (eError != PVRSRV_OK) + { + DisableSystemClocks(psSysData); + } } #endif @@ -124,6 +116,11 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData) #if defined(NO_HARDWARE) PVRSRV_ERROR eError; IMG_CPU_PHYADDR sCpuPAddr; +#else +#if defined(PVR_LINUX_DYNAMIC_SGX_RESOURCE_INFO) + struct resource *dev_res; + int dev_irq; +#endif #endif PVR_UNREFERENCED_PARAMETER(psSysData); @@ -134,7 +131,9 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData) #if defined(NO_HARDWARE) - eError = OSBaseAllocContigMemory(SYS_OMAP4430_SGX_REGS_SIZE, + gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE; + + eError = OSBaseAllocContigMemory(gsSGXDeviceMap.ui32RegsSize, &gsSGXRegsCPUVAddr, &sCpuPAddr); if(eError != PVRSRV_OK) @@ -143,7 +142,6 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData) } gsSGXDeviceMap.sRegsCpuPBase = sCpuPAddr; gsSGXDeviceMap.sRegsSysPBase = SysCpuPAddrToSysPAddr(gsSGXDeviceMap.sRegsCpuPBase); - gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE; #if defined(__linux__) gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr; @@ -152,7 +150,7 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData) gsSGXDeviceMap.pvRegsCpuVBase = IMG_NULL; #endif - OSMemSet(gsSGXRegsCPUVAddr, 0, SYS_OMAP4430_SGX_REGS_SIZE); + OSMemSet(gsSGXRegsCPUVAddr, 0, gsSGXDeviceMap.ui32RegsSize); @@ -160,13 +158,56 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData) gsSGXDeviceMap.ui32IRQ = 0; #else +#if defined(PVR_LINUX_DYNAMIC_SGX_RESOURCE_INFO) + + dev_res = platform_get_resource(gpsPVRLDMDev, IORESOURCE_MEM, 0); + if (dev_res == NULL) + { + PVR_DPF((PVR_DBG_ERROR, "%s: platform_get_resource failed", __FUNCTION__)); + return PVRSRV_ERROR_INVALID_DEVICE; + } + + dev_irq = platform_get_irq(gpsPVRLDMDev, 0); + if (dev_irq < 0) + { + PVR_DPF((PVR_DBG_ERROR, "%s: platform_get_irq failed (%d)", __FUNCTION__, -dev_irq)); + return PVRSRV_ERROR_INVALID_DEVICE; + } + + gsSGXDeviceMap.sRegsSysPBase.uiAddr = dev_res->start; + gsSGXDeviceMap.sRegsCpuPBase = + SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase); + PVR_TRACE(("SGX register base: 0x%lx", (unsigned long)gsSGXDeviceMap.sRegsCpuPBase.uiAddr)); + gsSGXDeviceMap.ui32RegsSize = (unsigned int)(dev_res->end - dev_res->start); + PVR_TRACE(("SGX register size: %d",gsSGXDeviceMap.ui32RegsSize)); + + gsSGXDeviceMap.ui32IRQ = dev_irq; + PVR_TRACE(("SGX IRQ: %d", gsSGXDeviceMap.ui32IRQ)); +#else gsSGXDeviceMap.sRegsSysPBase.uiAddr = SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE; gsSGXDeviceMap.sRegsCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase); gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE; gsSGXDeviceMap.ui32IRQ = SYS_OMAP4430_SGX_IRQ; +#endif +#if defined(SGX_OCP_REGS_ENABLED) + gsSGXRegsCPUVAddr = OSMapPhysToLin(gsSGXDeviceMap.sRegsCpuPBase, + gsSGXDeviceMap.ui32RegsSize, + PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY, + IMG_NULL); + + if (gsSGXRegsCPUVAddr == IMG_NULL) + { + PVR_DPF((PVR_DBG_ERROR,"SysLocateDevices: Failed to map SGX registers")); + return PVRSRV_ERROR_BAD_MAPPING; + } + + + gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr; + gpvOCPRegsLinAddr = gsSGXRegsCPUVAddr; +#endif #endif #if defined(PDUMP) @@ -184,7 +225,7 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData) } -IMG_CHAR *SysCreateVersionString(IMG_CPU_PHYADDR sRegRegion) +static IMG_CHAR *SysCreateVersionString(void) { static IMG_CHAR aszVersionString[100]; SYS_DATA *psSysData; @@ -193,8 +234,8 @@ IMG_CHAR *SysCreateVersionString(IMG_CPU_PHYADDR sRegRegion) #if !defined(NO_HARDWARE) IMG_VOID *pvRegsLinAddr; - pvRegsLinAddr = OSMapPhysToLin(sRegRegion, - SYS_OMAP4430_SGX_REGS_SIZE, + pvRegsLinAddr = OSMapPhysToLin(gsSGXDeviceMap.sRegsCpuPBase, + gsSGXDeviceMap.ui32RegsSize, PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY, IMG_NULL); if(!pvRegsLinAddr) @@ -286,17 +327,6 @@ PVRSRV_ERROR SysInitialise(IMG_VOID) return eError; } -#if !defined(PVR_NO_OMAP_TIMER) - TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE; - gpsSysData->pvSOCTimerRegisterKM = IMG_NULL; - gpsSysData->hSOCTimerRegisterOSMemHandle = 0; - OSReservePhys(TimerRegPhysBase, - 4, - PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED, - (IMG_VOID **)&gpsSysData->pvSOCTimerRegisterKM, - &gpsSysData->hSOCTimerRegisterOSMemHandle); -#endif - #if !defined(SGX_DYNAMIC_TIMING_INFO) psTimingInfo = &gsSGXDeviceMap.sTimingInfo; @@ -329,28 +359,6 @@ PVRSRV_ERROR SysInitialise(IMG_VOID) } SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV); -#if defined(SGX_OCP_REGS_ENABLED) - { - IMG_SYS_PHYADDR sOCPRegsSysPBase; - IMG_CPU_PHYADDR sOCPRegsCpuPBase; - - sOCPRegsSysPBase.uiAddr = SYS_OMAP4430_OCP_REGS_SYS_PHYS_BASE; - sOCPRegsCpuPBase = SysSysPAddrToCpuPAddr(sOCPRegsSysPBase); - - gpvOCPRegsLinAddr = OSMapPhysToLin(sOCPRegsCpuPBase, - SYS_OMAP4430_OCP_REGS_SIZE, - PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY, - IMG_NULL); - - if (gpvOCPRegsLinAddr == IMG_NULL) - { - PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to map OCP registers")); - return PVRSRV_ERROR_BAD_MAPPING; - } - SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_OCPREGS); - } -#endif - eError = SysPMRuntimeRegister(); if (eError != PVRSRV_OK) { @@ -419,8 +427,10 @@ PVRSRV_ERROR SysInitialise(IMG_VOID) psDeviceNode = psDeviceNode->psNext; } +#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) omap_device_set_rate(&gpsPVRLDMDev->dev, &gpsPVRLDMDev->dev, SYS_SGX_CLOCK_SPEED); +#endif eError = EnableSystemClocksWrap(gpsSysData); if (eError != PVRSRV_OK) @@ -457,6 +467,24 @@ PVRSRV_ERROR SysInitialise(IMG_VOID) DisableSGXClocks(gpsSysData); #endif +#if !defined(PVR_NO_OMAP_TIMER) +#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA) + TimerRegPhysBase = gsSysSpecificData.sTimerRegPhysBase; +#else + TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE; +#endif + gpsSysData->pvSOCTimerRegisterKM = IMG_NULL; + gpsSysData->hSOCTimerRegisterOSMemHandle = 0; + if (TimerRegPhysBase.uiAddr != 0) + { + OSReservePhys(TimerRegPhysBase, + 4, + PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED, + (IMG_VOID **)&gpsSysData->pvSOCTimerRegisterKM, + &gpsSysData->hSOCTimerRegisterOSMemHandle); + } +#endif + return PVRSRV_OK; } @@ -495,14 +523,14 @@ PVRSRV_ERROR SysFinalise(IMG_VOID) #if defined(__linux__) - gpsSysData->pszVersionString = SysCreateVersionString(gsSGXDeviceMap.sRegsCpuPBase); + gpsSysData->pszVersionString = SysCreateVersionString(); if (!gpsSysData->pszVersionString) { PVR_DPF((PVR_DBG_ERROR,"SysFinalise: Failed to create a system version string")); } else { - PVR_DPF((PVR_DBG_WARNING, "SysFinalise: Version string: %s", gpsSysData->pszVersionString)); + PVR_TRACE(("SysFinalise: Version string: %s", gpsSysData->pszVersionString)); } #endif @@ -521,6 +549,14 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData) { PVRSRV_ERROR eError; + if(gpsSysData->pvSOCTimerRegisterKM) + { + OSUnReservePhys(gpsSysData->pvSOCTimerRegisterKM, + 4, + PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED, + gpsSysData->hSOCTimerRegisterOSMemHandle); + } + #if defined(SYS_USING_INTERRUPTS) if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LISR)) { @@ -571,22 +607,11 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData) if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: Failed to unregister with OSPM!")); - (IMG_VOID)SysDeinitialise(gpsSysData); gpsSysData = IMG_NULL; return eError; } } -#if defined(SGX_OCP_REGS_ENABLED) - if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_OCPREGS)) - { - OSUnMapPhysToLin(gpvOCPRegsLinAddr, - SYS_OMAP4430_OCP_REGS_SIZE, - PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY, - IMG_NULL); - } -#endif - if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_SYSCLOCKS)) @@ -604,21 +629,26 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData) } } - if(gpsSysData->pvSOCTimerRegisterKM) - { - OSUnReservePhys(gpsSysData->pvSOCTimerRegisterKM, - 4, - PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED, - gpsSysData->hSOCTimerRegisterOSMemHandle); - } - SysDeinitialiseCommon(gpsSysData); -#if defined(NO_HARDWARE) - if(SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV)) +#if defined(NO_HARDWARE) || defined(SGX_OCP_REGS_ENABLED) + if(gsSGXRegsCPUVAddr != IMG_NULL) { +#if defined(NO_HARDWARE) OSBaseFreeContigMemory(SYS_OMAP4430_SGX_REGS_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase); +#else +#if defined(SGX_OCP_REGS_ENABLED) + OSUnMapPhysToLin(gsSGXRegsCPUVAddr, + gsSGXDeviceMap.ui32RegsSize, + PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY, + IMG_NULL); + + gpvOCPRegsLinAddr = IMG_NULL; +#endif +#endif + gsSGXRegsCPUVAddr = IMG_NULL; + gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr; } #endif @@ -740,14 +770,41 @@ IMG_UINT32 SysGetInterruptSource(SYS_DATA *psSysData, IMG_VOID SysClearInterrupts(SYS_DATA* psSysData, IMG_UINT32 ui32ClearBits) { - PVR_UNREFERENCED_PARAMETER(psSysData); PVR_UNREFERENCED_PARAMETER(ui32ClearBits); - +#if defined(NO_HARDWARE) + PVR_UNREFERENCED_PARAMETER(psSysData); +#else +#if defined(SGX_OCP_NO_INT_BYPASS) + OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_IRQSTATUS_2, 0x1); +#endif - OSReadHWReg(((PVRSRV_SGXDEV_INFO *)gpsSGXDevNode->pvDevice)->pvRegsBaseKM, - EUR_CR_EVENT_HOST_CLEAR); + OSReadHWReg(((PVRSRV_SGXDEV_INFO *)gpsSGXDevNode->pvDevice)->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR); +#endif } +#if defined(SGX_OCP_NO_INT_BYPASS) +IMG_VOID SysEnableSGXInterrupts(SYS_DATA *psSysData) +{ + SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *)psSysData->pvSysSpecificData; + if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_ENABLE_LISR) && !SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED)) + { + OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_IRQSTATUS_2, 0x1); + OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_IRQENABLE_SET_2, 0x1); + SYS_SPECIFIC_DATA_SET(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED); + } +} + +IMG_VOID SysDisableSGXInterrupts(SYS_DATA *psSysData) +{ + SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *)psSysData->pvSysSpecificData; + + if (SYS_SPECIFIC_DATA_TEST(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED)) + { + OSWriteHWReg(gpvOCPRegsLinAddr, EUR_CR_OCP_IRQENABLE_CLR_2, 0x1); + SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, SYS_SPECIFIC_DATA_IRQ_ENABLED); + } +} +#endif PVRSRV_ERROR SysSystemPrePowerState(PVRSRV_SYS_POWER_STATE eNewPowerState) { diff --git a/drivers/gpu/pvr/omap4/sysconfig.h b/drivers/gpu/pvr/omap4/sysconfig.h index 46930b54da9..8e84def99c0 100644 --- a/drivers/gpu/pvr/omap4/sysconfig.h +++ b/drivers/gpu/pvr/omap4/sysconfig.h @@ -27,8 +27,6 @@ #if !defined(__SOCCONFIG_H__) #define __SOCCONFIG_H__ -#include "syscommon.h" - #define VS_PRODUCT_NAME "OMAP4" #if defined(SGX540) && (SGX_CORE_REV == 120) @@ -51,9 +49,13 @@ #define SYS_OMAP4430_SGX_IRQ 53 -#define SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE 0x48088038 -#define SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE 0x4808803C -#define SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE 0x48088054 +#define SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE 0x48088038 +#define SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE 0x4808803C +#define SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE 0x48088054 + +#if defined(__linux__) +#define SYS_SGX_DEV_NAME "omap_gpu" +#endif #endif diff --git a/drivers/gpu/pvr/omap4/syslocal.h b/drivers/gpu/pvr/omap4/syslocal.h index bc9a078fc43..e07c51fda75 100644 --- a/drivers/gpu/pvr/omap4/syslocal.h +++ b/drivers/gpu/pvr/omap4/syslocal.h @@ -48,16 +48,52 @@ #endif #endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) +#if !defined(LDM_PLATFORM) +#error "LDM_PLATFORM must be set" +#endif +#define PVR_LINUX_DYNAMIC_SGX_RESOURCE_INFO +#include <linux/platform_device.h> +#endif + +#if ((defined(DEBUG) || defined(TIMING)) && \ + (LINUX_VERSION_CODE == KERNEL_VERSION(2,6,34))) && \ + !defined(PVR_NO_OMAP_TIMER) +#define PVR_OMAP4_TIMING_PRCM +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) +#include <plat/gpu.h> +#if !defined(PVR_NO_OMAP_TIMER) +#define PVR_OMAP_USE_DM_TIMER_API +#include <plat/dmtimer.h> +#endif +#endif + +#if !defined(PVR_NO_OMAP_TIMER) +#define PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA +#endif #endif +#if !defined(NO_HARDWARE) && \ + defined(SYS_USING_INTERRUPTS) && \ + defined(SGX540) +#define SGX_OCP_REGS_ENABLED +#endif + +#if defined(__linux__) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) && defined(SGX_OCP_REGS_ENABLED) +#define SGX_OCP_NO_INT_BYPASS +#endif +#endif + #if defined (__cplusplus) extern "C" { #endif -IMG_CHAR *SysCreateVersionString(IMG_CPU_PHYADDR sRegRegion); - IMG_VOID DisableSystemClocks(SYS_DATA *psSysData); PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData); @@ -78,6 +114,9 @@ PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData); #define SYS_SPECIFIC_DATA_PM_DISABLE_SYSCLOCKS 0x00000400 #define SYS_SPECIFIC_DATA_ENABLE_OCPREGS 0x00000800 #define SYS_SPECIFIC_DATA_ENABLE_PM_RUNTIME 0x00001000 +#if defined(SGX_OCP_REGS_ENABLED) && defined(SGX_OCP_NO_INT_BYPASS) +#define SYS_SPECIFIC_DATA_IRQ_ENABLED 0x00002000 +#endif #define SYS_SPECIFIC_DATA_SET(psSysSpecData, flag) ((IMG_VOID)((psSysSpecData)->ui32SysSpecificData |= (flag))) @@ -90,6 +129,9 @@ typedef struct _SYS_SPECIFIC_DATA_TAG_ IMG_UINT32 ui32SysSpecificData; PVRSRV_DEVICE_NODE *psSGXDevNode; IMG_BOOL bSGXInitComplete; +#if defined(PVR_OMAP_TIMER_BASE_IN_SYS_SPEC_DATA) + IMG_CPU_PHYADDR sTimerRegPhysBase; +#endif #if !defined(__linux__) IMG_BOOL bSGXClocksEnabled; #endif @@ -107,19 +149,26 @@ typedef struct _SYS_SPECIFIC_DATA_TAG_ atomic_t sNotifyLockCPU; IMG_BOOL bCallVDD2PostFunc; #endif - struct clk *psCORE_CK; - struct clk *psSGX_FCK; - struct clk *psSGX_ICK; - struct clk *psMPU_CK; #if defined(DEBUG) || defined(TIMING) struct clk *psGPT11_FCK; struct clk *psGPT11_ICK; #endif +#if defined(PVR_OMAP_USE_DM_TIMER_API) + struct omap_dm_timer *psGPTimer; +#endif #endif } SYS_SPECIFIC_DATA; extern SYS_SPECIFIC_DATA *gpsSysSpecificData; +#if defined(SGX_OCP_REGS_ENABLED) && defined(SGX_OCP_NO_INT_BYPASS) +IMG_VOID SysEnableSGXInterrupts(SYS_DATA* psSysData); +IMG_VOID SysDisableSGXInterrupts(SYS_DATA* psSysData); +#else +#define SysEnableSGXInterrupts(psSysData) +#define SysDisableSGXInterrupts(psSysData) +#endif + #if defined(SYS_CUSTOM_POWERLOCK_WRAP) IMG_BOOL WrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData); IMG_VOID UnwrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData); diff --git a/drivers/gpu/pvr/omap4/sysutils_linux.c b/drivers/gpu/pvr/omap4/sysutils_linux.c index 52ae877f05e..f7c3ac11424 100644 --- a/drivers/gpu/pvr/omap4/sysutils_linux.c +++ b/drivers/gpu/pvr/omap4/sysutils_linux.c @@ -41,16 +41,6 @@ #include <linux/platform_device.h> #include <linux/pm_runtime.h> -#if !defined(PVR_LINUX_USING_WORKQUEUES) -#error "PVR_LINUX_USING_WORKQUEUES must be defined" -#endif - -#if ((defined(DEBUG) || defined(TIMING)) && \ - (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34))) && \ - !defined(PVR_NO_OMAP_TIMER) -#define PVR_OMAP4_TIMING_PRCM -#endif - #define ONE_MHZ 1000000 #define HZ_TO_MHZ(m) ((m) / ONE_MHZ) @@ -60,7 +50,7 @@ #define SGX_PARENT_CLOCK "core_ck" #endif -#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) +#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) extern struct platform_device *gpsPVRLDMDev; #endif @@ -134,17 +124,9 @@ IMG_VOID SysGetSGXTimingInformation(SGX_TIMING_INFORMATION *psTimingInfo) { IMG_UINT32 rate; -#if defined(NO_HARDWARE) rate = SYS_SGX_CLOCK_SPEED; -#else +#if !defined(NO_HARDWARE) PVR_ASSERT(atomic_read(&gpsSysSpecificData->sSGXClocksEnabled) != 0); - -#if defined(OMAP4_PRCM_ENABLE) - rate = clk_get_rate(gpsSysSpecificData->psSGX_FCK); -#else - rate = SYS_SGX_CLOCK_SPEED; -#endif - PVR_ASSERT(rate != 0); #endif psTimingInfo->ui32CoreClockSpeed = rate; psTimingInfo->ui32HWRecoveryFreq = scale_prop_to_SGX_clock(SYS_SGX_HWRECOVERY_TIMEOUT_FREQ, rate); @@ -161,11 +143,6 @@ PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData) { #if !defined(NO_HARDWARE) SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; -#if defined(OMAP4_PRCM_ENABLE) - long lNewRate; - long lRate; - IMG_INT res; -#endif if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0) @@ -175,61 +152,18 @@ PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData) PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks")); -#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) - pm_runtime_get_sync(&gpsPVRLDMDev->dev); -#endif - -#if defined(OMAP4_PRCM_ENABLE) - -#if defined(DEBUG) - { - IMG_UINT32 rate = clk_get_rate(psSysSpecData->psMPU_CK); - PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: CPU Clock is %dMhz", HZ_TO_MHZ(rate))); - } -#endif - - res = clk_enable(psSysSpecData->psSGX_FCK); - if (res < 0) +#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) { - PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res)); - return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; - } - res = clk_enable(psSysSpecData->psSGX_ICK); - if (res < 0) - { - PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX interface clock (%d)", res)); - - clk_disable(psSysSpecData->psSGX_FCK); - return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; - } - - lNewRate = clk_round_rate(psSysSpecData->psSGX_FCK, SYS_SGX_CLOCK_SPEED + ONE_MHZ); - if (lNewRate <= 0) - { - PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't round SGX functional clock rate")); - return PVRSRV_ERROR_UNABLE_TO_ROUND_CLOCK_RATE; - } - - - lRate = clk_get_rate(psSysSpecData->psSGX_FCK); - if (lRate != lNewRate) - { - res = clk_set_rate(psSysSpecData->psSGX_FCK, lNewRate); + int res = pm_runtime_get_sync(&gpsPVRLDMDev->dev); if (res < 0) { - PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Couldn't set SGX functional clock rate (%d)", res)); + PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: pm_runtime_get_sync failed (%d)", -res)); + return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK; } } - -#if defined(DEBUG) - { - IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK); - PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate))); - } #endif - -#endif + SysEnableSGXInterrupts(psSysData); atomic_set(&psSysSpecData->sSGXClocksEnabled, 1); @@ -254,21 +188,17 @@ IMG_VOID DisableSGXClocks(SYS_DATA *psSysData) PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks")); -#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) - pm_runtime_put_sync(&gpsPVRLDMDev->dev); -#endif + SysDisableSGXInterrupts(psSysData); -#if defined(OMAP4_PRCM_ENABLE) - if (psSysSpecData->psSGX_ICK) +#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) { - clk_disable(psSysSpecData->psSGX_ICK); - } - - if (psSysSpecData->psSGX_FCK) - { - clk_disable(psSysSpecData->psSGX_FCK); + int res = pm_runtime_put_sync(&gpsPVRLDMDev->dev); + if (res < 0) + { + PVR_DPF((PVR_DBG_ERROR, "DisableSGXClocks: pm_runtime_put_sync failed (%d)", -res)); + } } -#endif +#endif atomic_set(&psSysSpecData->sSGXClocksEnabled, 0); @@ -278,86 +208,78 @@ IMG_VOID DisableSGXClocks(SYS_DATA *psSysData) #endif } -PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) +#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER) +#if defined(PVR_OMAP_USE_DM_TIMER_API) +#define GPTIMER_TO_USE 11 +static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { - SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; -#if (defined(OMAP4_PRCM_ENABLE) || defined(PVR_OMAP4_TIMING_PRCM)) - struct clk *psCLK; - IMG_INT res; -#endif -#if defined(PVR_OMAP4_TIMING_PRCM) - struct clk *sys_ck; - IMG_INT rate; -#endif - PVRSRV_ERROR eError; + PVR_ASSERT(psSysSpecData->psGPTimer == NULL); -#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER) - IMG_CPU_PHYADDR TimerRegPhysBase; - IMG_HANDLE hTimerEnable; - IMG_UINT32 *pui32TimerEnable; -#endif - PVR_TRACE(("EnableSystemClocks: Enabling System Clocks")); + psSysSpecData->psGPTimer = omap_dm_timer_request_specific(GPTIMER_TO_USE); + if (psSysSpecData->psGPTimer == NULL) + { - if (!psSysSpecData->bSysClocksOneTimeInit) + PVR_DPF((PVR_DBG_WARNING, "%s: omap_dm_timer_request_specific failed", __FUNCTION__)); + return PVRSRV_ERROR_CLOCK_REQUEST_FAILED; + } + + + omap_dm_timer_set_source(psSysSpecData->psGPTimer, OMAP_TIMER_SRC_SYS_CLK); + omap_dm_timer_enable(psSysSpecData->psGPTimer); + + + omap_dm_timer_set_load_start(psSysSpecData->psGPTimer, 1, 0); + + omap_dm_timer_start(psSysSpecData->psGPTimer); + + + psSysSpecData->sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE; + + return PVRSRV_OK; +} + +static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) +{ + if (psSysSpecData->psGPTimer != NULL) { - mutex_init(&psSysSpecData->sPowerLock); - atomic_set(&psSysSpecData->sSGXClocksEnabled, 0); + (void) omap_dm_timer_stop(psSysSpecData->psGPTimer); -#if defined(OMAP4_PRCM_ENABLE) - psCLK = clk_get(NULL, SGX_PARENT_CLOCK); - if (IS_ERR(psCLK)) - { - PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get Core Clock")); - goto ExitError; - } - psSysSpecData->psCORE_CK = psCLK; + omap_dm_timer_disable(psSysSpecData->psGPTimer); - psCLK = clk_get(NULL, "sgx_fck"); - if (IS_ERR(psCLK)) - { - PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get SGX Functional Clock")); - goto ExitError; - } - psSysSpecData->psSGX_FCK = psCLK; + omap_dm_timer_free(psSysSpecData->psGPTimer); - psCLK = clk_get(NULL, "sgx_ick"); - if (IS_ERR(psCLK)) - { - PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock")); - goto ExitError; - } - psSysSpecData->psSGX_ICK = psCLK; + psSysSpecData->sTimerRegPhysBase.uiAddr = 0; -#if defined(DEBUG) - psCLK = clk_get(NULL, "mpu_ck"); - if (IS_ERR(psCLK)) - { - PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get MPU Clock")); - goto ExitError; - } - psSysSpecData->psMPU_CK = psCLK; + psSysSpecData->psGPTimer = NULL; + } + +} +#else +static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) +{ +#if defined(PVR_OMAP4_TIMING_PRCM) + struct clk *psCLK; + IMG_INT res; + struct clk *sys_ck; + IMG_INT rate; #endif - res = clk_set_parent(psSysSpecData->psSGX_FCK, psSysSpecData->psCORE_CK); - if (res < 0) - { - PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set SGX parent clock (%d)", res)); - goto ExitError; - } -#endif + PVRSRV_ERROR eError; - psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE; - } + IMG_CPU_PHYADDR sTimerRegPhysBase; + IMG_HANDLE hTimerEnable; + IMG_UINT32 *pui32TimerEnable; + + PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0); -#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER) #if defined(PVR_OMAP4_TIMING_PRCM) psCLK = clk_get(NULL, "gpt11_fck"); if (IS_ERR(psCLK)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock")); - goto ExitUnRegisterConstraintNotifications; + goto ExitError; } psSysSpecData->psGPT11_FCK = psCLK; @@ -365,7 +287,7 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) if (IS_ERR(psCLK)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock")); - goto ExitUnRegisterConstraintNotifications; + goto ExitError; } psSysSpecData->psGPT11_ICK = psCLK; @@ -373,7 +295,7 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) if (IS_ERR(sys_ck)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock")); - goto ExitUnRegisterConstraintNotifications; + goto ExitError; } if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck) @@ -383,7 +305,7 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res)); - goto ExitUnRegisterConstraintNotifications; + goto ExitError; } } @@ -394,7 +316,7 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res)); - goto ExitUnRegisterConstraintNotifications; + goto ExitError; } res = clk_enable(psSysSpecData->psGPT11_ICK); @@ -406,8 +328,8 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) #endif - TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE; - pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase, + sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE; + pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, &hTimerEnable); @@ -432,8 +354,8 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) hTimerEnable); - TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE; - pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase, + sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE; + pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, &hTimerEnable); @@ -452,48 +374,36 @@ PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, hTimerEnable); -#endif + psSysSpecData->sTimerRegPhysBase = sTimerRegPhysBase; eError = PVRSRV_OK; + goto Exit; -#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER) ExitDisableGPT11ICK: #if defined(PVR_OMAP4_TIMING_PRCM) clk_disable(psSysSpecData->psGPT11_ICK); ExitDisableGPT11FCK: clk_disable(psSysSpecData->psGPT11_FCK); -ExitUnRegisterConstraintNotifications: -#endif -#endif -#if defined(OMAP4_PRCM_ENABLE) ExitError: #endif - eError = PVRSRV_ERROR_DISABLE_CLOCK_FAILURE; + eError = PVRSRV_ERROR_CLOCK_REQUEST_FAILED; Exit: return eError; } -IMG_VOID DisableSystemClocks(SYS_DATA *psSysData) +static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { -#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER) -#if defined(PVR_OMAP4_TIMING_PRCM) - SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; -#endif - IMG_CPU_PHYADDR TimerRegPhysBase; IMG_HANDLE hTimerDisable; IMG_UINT32 *pui32TimerDisable; -#endif - PVR_TRACE(("DisableSystemClocks: Disabling System Clocks")); - - - DisableSGXClocks(psSysData); + if (psSysSpecData->sTimerRegPhysBase.uiAddr == 0) + { + return; + } -#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER) - TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE; - pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase, + pui32TimerDisable = OSMapPhysToLin(psSysSpecData->sTimerRegPhysBase, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, &hTimerDisable); @@ -512,17 +422,61 @@ IMG_VOID DisableSystemClocks(SYS_DATA *psSysData) hTimerDisable); } + psSysSpecData->sTimerRegPhysBase.uiAddr = 0; + #if defined(PVR_OMAP4_TIMING_PRCM) clk_disable(psSysSpecData->psGPT11_ICK); clk_disable(psSysSpecData->psGPT11_FCK); #endif +} +#endif +#else +static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) +{ + PVR_UNREFERENCED_PARAMETER(psSysSpecData); + + return PVRSRV_OK; +} +static void ReleaseGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) +{ + PVR_UNREFERENCED_PARAMETER(psSysSpecData); +} #endif + +PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData) +{ + SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; + + PVR_TRACE(("EnableSystemClocks: Enabling System Clocks")); + + if (!psSysSpecData->bSysClocksOneTimeInit) + { + mutex_init(&psSysSpecData->sPowerLock); + + atomic_set(&psSysSpecData->sSGXClocksEnabled, 0); + + psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE; + } + + return AcquireGPTimer(psSysSpecData); +} + +IMG_VOID DisableSystemClocks(SYS_DATA *psSysData) +{ + SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData; + + PVR_TRACE(("DisableSystemClocks: Disabling System Clocks")); + + + DisableSGXClocks(psSysData); + + ReleaseGPTimer(psSysSpecData); } PVRSRV_ERROR SysPMRuntimeRegister(void) { -#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) +#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) pm_runtime_enable(&gpsPVRLDMDev->dev); #endif return PVRSRV_OK; @@ -530,7 +484,7 @@ PVRSRV_ERROR SysPMRuntimeRegister(void) PVRSRV_ERROR SysPMRuntimeUnregister(void) { -#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM) +#if defined(LDM_PLATFORM) && !defined(PVR_DRI_DRM_NOT_PCI) pm_runtime_disable(&gpsPVRLDMDev->dev); #endif return PVRSRV_OK; diff --git a/drivers/gpu/pvr/osfunc.c b/drivers/gpu/pvr/osfunc.c index 9a264d23a87..2bcf0ed40ce 100644 --- a/drivers/gpu/pvr/osfunc.c +++ b/drivers/gpu/pvr/osfunc.c @@ -115,6 +115,15 @@ PVRSRV_ERROR OSAllocMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOI return PVRSRV_OK; } +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)) + +static inline int is_vmalloc_addr(const void *pvCpuVAddr) +{ + unsigned long lAddr = (unsigned long)pvCpuVAddr; + return lAddr >= VMALLOC_START && lAddr < VMALLOC_END; +} + +#endif #if !defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) PVRSRV_ERROR OSFreeMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID pvCpuVAddr, IMG_HANDLE hBlockAlloc) @@ -2950,6 +2959,29 @@ IMG_VOID OSFlushCPUCacheKM(IMG_VOID) #endif } +static inline size_t pvr_dmac_range_len(const void *pvStart, const void *pvEnd) +{ + return (size_t)((char *)pvEnd - (char *)pvStart); +} + +static void pvr_dmac_inv_range(const void *pvStart, const void *pvEnd) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)) + dmac_inv_range(pvStart, pvEnd); +#else + dmac_map_area(pvStart, pvr_dmac_range_len(pvStart, pvEnd), DMA_FROM_DEVICE); +#endif +} + +static void pvr_dmac_clean_range(const void *pvStart, const void *pvEnd) +{ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)) + dmac_clean_range(pvStart, pvEnd); +#else + dmac_map_area(pvStart, pvr_dmac_range_len(pvStart, pvEnd), DMA_TO_DEVICE); +#endif +} + IMG_BOOL OSFlushCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, IMG_VOID *pvRangeAddrStart, IMG_UINT32 ui32Length) @@ -2963,7 +2995,7 @@ IMG_BOOL OSCleanCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, IMG_UINT32 ui32Length) { return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length, - dmac_clean_range, outer_clean_range); + pvr_dmac_clean_range, outer_clean_range); } IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, @@ -2971,7 +3003,7 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, IMG_UINT32 ui32Length) { return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length, - dmac_inv_range, outer_inv_range); + pvr_dmac_inv_range, outer_inv_range); } #else @@ -2993,7 +3025,8 @@ IMG_BOOL OSFlushCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, IMG_VOID *pvRangeAddrStart, IMG_UINT32 ui32Length) { - dma_cache_wback_inv((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); + if (ui32Length) + dma_cache_wback_inv((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); return IMG_TRUE; } @@ -3001,7 +3034,8 @@ IMG_BOOL OSCleanCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, IMG_VOID *pvRangeAddrStart, IMG_UINT32 ui32Length) { - dma_cache_wback((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); + if (ui32Length) + dma_cache_wback((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); return IMG_TRUE; } @@ -3009,7 +3043,8 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle, IMG_VOID *pvRangeAddrStart, IMG_UINT32 ui32Length) { - dma_cache_inv((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); + if (ui32Length) + dma_cache_inv((IMG_UINTPTR_T)pvRangeAddrStart, ui32Length); return IMG_TRUE; } diff --git a/drivers/gpu/pvr/pdump/dbgdriv.c b/drivers/gpu/pvr/pdump/dbgdriv.c index a1ca244f5f7..f8f635fd1e6 100644 --- a/drivers/gpu/pvr/pdump/dbgdriv.c +++ b/drivers/gpu/pvr/pdump/dbgdriv.c @@ -707,7 +707,7 @@ void MonoOut(IMG_CHAR * pszString,IMG_BOOL bNewLine) PVR_UNREFERENCED_PARAMETER(bNewLine); #else - IMG_UINT32 i; + IMG_UINT32 i; IMG_CHAR * pScreen; pScreen = (IMG_CHAR *) DBGDRIV_MONOBASE; @@ -842,10 +842,10 @@ static IMG_UINT32 WriteExpandingBuffer(PDBG_STREAM psStream,IMG_UINT8 * pui8InBu } IMG_VOID * IMG_CALLCONV DBGDrivCreateStream(IMG_CHAR * pszName, - IMG_UINT32 ui32CapMode, - IMG_UINT32 ui32OutMode, + IMG_UINT32 ui32CapMode, + IMG_UINT32 ui32OutMode, IMG_UINT32 ui32Flags, - IMG_UINT32 ui32Size) + IMG_UINT32 ui32Size) { PDBG_STREAM psStream; PDBG_STREAM psInitStream; diff --git a/drivers/gpu/pvr/pdump/dbgdriv.h b/drivers/gpu/pvr/pdump/dbgdriv.h index a285d0d919b..dc75f88f160 100644 --- a/drivers/gpu/pvr/pdump/dbgdriv.h +++ b/drivers/gpu/pvr/pdump/dbgdriv.h @@ -29,9 +29,9 @@ #define BUFFER_SIZE 64*PAGESIZE -#define DBGDRIV_VERSION 0x100 -#define MAX_PROCESSES 2 -#define BLOCK_USED 0x01 +#define DBGDRIV_VERSION 0x100 +#define MAX_PROCESSES 2 +#define BLOCK_USED 0x01 #define BLOCK_LOCKED 0x02 #define DBGDRIV_MONOBASE 0x000B0000 @@ -39,10 +39,10 @@ extern IMG_VOID * g_pvAPIMutex; IMG_VOID * IMG_CALLCONV DBGDrivCreateStream(IMG_CHAR * pszName, - IMG_UINT32 ui32CapMode, - IMG_UINT32 ui32OutMode, + IMG_UINT32 ui32CapMode, + IMG_UINT32 ui32OutMode, IMG_UINT32 ui32Flags, - IMG_UINT32 ui32Pages); + IMG_UINT32 ui32Pages); IMG_VOID IMG_CALLCONV DBGDrivDestroyStream(PDBG_STREAM psStream); IMG_VOID * IMG_CALLCONV DBGDrivFindStream(IMG_CHAR * pszName, IMG_BOOL bResetStream); IMG_UINT32 IMG_CALLCONV DBGDrivWriteString(PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Level); diff --git a/drivers/gpu/pvr/pdump/dbgdriv_ioctl.h b/drivers/gpu/pvr/pdump/dbgdriv_ioctl.h index 8cef6ac78a8..68492495115 100644 --- a/drivers/gpu/pvr/pdump/dbgdriv_ioctl.h +++ b/drivers/gpu/pvr/pdump/dbgdriv_ioctl.h @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/pvr/pdump/handle.c b/drivers/gpu/pvr/pdump/handle.c index dceeab886c1..8ba44df7055 100644 --- a/drivers/gpu/pvr/pdump/handle.c +++ b/drivers/gpu/pvr/pdump/handle.c @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -68,7 +68,7 @@ PDBG_STREAM SID2PStream(IMG_SID hStream) } else { - return (PDBG_STREAM)IMG_NULL; + return (PDBG_STREAM)IMG_NULL; } } diff --git a/drivers/gpu/pvr/pdump/hostfunc.c b/drivers/gpu/pvr/pdump/hostfunc.c index 64b20cc37b8..5eb8e1cc91a 100644 --- a/drivers/gpu/pvr/pdump/hostfunc.c +++ b/drivers/gpu/pvr/pdump/hostfunc.c @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -29,13 +29,17 @@ #include <linux/module.h> #include <linux/fs.h> #include <linux/kernel.h> +#include <linux/slab.h> #include <linux/mm.h> #include <linux/string.h> #include <asm/page.h> #include <linux/vmalloc.h> +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,15)) #include <linux/mutex.h> +#else +#include <asm/semaphore.h> +#endif #include <linux/hardirq.h> -#include <linux/slab.h> #if defined(SUPPORT_DBGDRV_EVENT_OBJECTS) #include <linux/sched.h> @@ -51,13 +55,13 @@ #include "hostfunc.h" #include "dbgdriv.h" -#if defined(DEBUG) && !defined(SUPPORT_DRI_DRM) -IMG_UINT32 gPVRDumpDebugLevel = (DBGPRIV_FATAL | DBGPRIV_ERROR | DBGPRIV_WARNING); +#if defined(MODULE) && defined(DEBUG) && !defined(SUPPORT_DRI_DRM) +IMG_UINT32 gPVRDebugLevel = (DBGPRIV_FATAL | DBGPRIV_ERROR | DBGPRIV_WARNING); #define PVR_STRING_TERMINATOR '\0' #define PVR_IS_FILE_SEPARATOR(character) ( ((character) == '\\') || ((character) == '/') ) -void PVRSRVDumpDebugPrintf ( +void PVRSRVDebugPrintf ( IMG_UINT32 ui32DebugLevel, const IMG_CHAR* pszFileName, IMG_UINT32 ui32Line, @@ -79,7 +83,7 @@ void PVRSRVDumpDebugPrintf ( bTrace = (IMG_BOOL)(ui32DebugLevel & DBGPRIV_CALLTRACE) ? IMG_TRUE : IMG_FALSE; - if (gPVRDumpDebugLevel & ui32DebugLevel) + if (gPVRDebugLevel & ui32DebugLevel) { va_list vaArgs; static char szBuffer[256]; @@ -131,7 +135,7 @@ void PVRSRVDumpDebugPrintf ( vsprintf (&szBuffer[strlen(szBuffer)], pszFormat, vaArgs); - if (bTrace == IMG_FALSE) + if (bTrace == IMG_FALSE) { sprintf (&szBuffer[strlen(szBuffer)], " [%d, %s]", (int)ui32Line, pszFileName); } diff --git a/drivers/gpu/pvr/pdump/hostfunc.h b/drivers/gpu/pvr/pdump/hostfunc.h index 42733d7c131..acfc439db0a 100644 --- a/drivers/gpu/pvr/pdump/hostfunc.h +++ b/drivers/gpu/pvr/pdump/hostfunc.h @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/pvr/pdump/hotkey.c b/drivers/gpu/pvr/pdump/hotkey.c index 48853c79537..2d82b6cf6d9 100644 --- a/drivers/gpu/pvr/pdump/hotkey.c +++ b/drivers/gpu/pvr/pdump/hotkey.c @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/pvr/pdump/hotkey.h b/drivers/gpu/pvr/pdump/hotkey.h index d9c9458da74..942d2daa3a9 100644 --- a/drivers/gpu/pvr/pdump/hotkey.h +++ b/drivers/gpu/pvr/pdump/hotkey.h @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/pvr/pdump/ioctl.c b/drivers/gpu/pvr/pdump/ioctl.c index e646c4f9324..1d291468526 100644 --- a/drivers/gpu/pvr/pdump/ioctl.c +++ b/drivers/gpu/pvr/pdump/ioctl.c @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -194,7 +194,7 @@ static IMG_UINT32 DBGDIOCDrivWrite2(IMG_VOID * pvInBuffer, IMG_VOID * pvOutBuffe { IMG_UINT32 * pui32BytesCopied; PDBG_IN_WRITE psInParams; - PDBG_STREAM psStream; + PDBG_STREAM psStream; psInParams = (PDBG_IN_WRITE) pvInBuffer; pui32BytesCopied = (IMG_UINT32 *) pvOutBuffer; diff --git a/drivers/gpu/pvr/pdump/linuxsrv.h b/drivers/gpu/pvr/pdump/linuxsrv.h index 671622fa8b4..4888cd04214 100644 --- a/drivers/gpu/pvr/pdump/linuxsrv.h +++ b/drivers/gpu/pvr/pdump/linuxsrv.h @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -31,7 +31,7 @@ typedef struct tagIOCTL_PACKAGE { IMG_UINT32 ui32Cmd; IMG_UINT32 ui32Size; - IMG_VOID *pInBuffer; + IMG_VOID *pInBuffer; IMG_UINT32 ui32InBufferSize; IMG_VOID *pOutBuffer; IMG_UINT32 ui32OutBufferSize; diff --git a/drivers/gpu/pvr/pdump/main.c b/drivers/gpu/pvr/pdump/main.c index 69c0d9b1a97..45d041b087f 100644 --- a/drivers/gpu/pvr/pdump/main.c +++ b/drivers/gpu/pvr/pdump/main.c @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -116,7 +116,7 @@ IMG_VOID DBGDrvGetServiceTable(IMG_VOID **fn_table) #if defined(SUPPORT_DRI_DRM) void dbgdrv_cleanup(void) #else -void __exit dbgdrv_cleanup_module(void) +static void __exit dbgdrv_cleanup(void) #endif { #if !defined(SUPPORT_DRI_DRM) @@ -136,7 +136,7 @@ void __exit dbgdrv_cleanup_module(void) #if defined(SUPPORT_DRI_DRM) IMG_INT dbgdrv_init(void) #else -int __init dbgdrv_init_module(void) +static int __init dbgdrv_init(void) #endif { #if (defined(LDM_PLATFORM) || defined(LDM_PCI)) && !defined(SUPPORT_DRI_DRM) @@ -240,6 +240,7 @@ long dbgdrv_ioctl(struct file *file, unsigned int ioctlCmd, unsigned long arg) goto init_failed; } + cmd = MAKEIOCTLINDEX(pIP->ui32Cmd) - DEBUG_SERVICE_IOCTL_BASE - 1; if(pIP->ui32Cmd == DEBUG_SERVICE_READ) @@ -310,5 +311,7 @@ IMG_VOID DefineHotKey (IMG_UINT32 ui32ScanCode, IMG_UINT32 ui32ShiftState, PHOTK EXPORT_SYMBOL(DBGDrvGetServiceTable); -module_init(dbgdrv_init_module); -module_exit(dbgdrv_cleanup_module); +#if !defined(SUPPORT_DRI_DRM) +subsys_initcall(dbgdrv_init); +module_exit(dbgdrv_cleanup); +#endif diff --git a/drivers/gpu/pvr/perproc.c b/drivers/gpu/pvr/perproc.c index 1753388b1bb..eb73166bb32 100644 --- a/drivers/gpu/pvr/perproc.c +++ b/drivers/gpu/pvr/perproc.c @@ -127,7 +127,10 @@ PVRSRV_ERROR PVRSRVPerProcessDataConnect(IMG_UINT32 ui32PID, IMG_UINT32 ui32Flag IMG_HANDLE hBlockAlloc; PVRSRV_ERROR eError = PVRSRV_OK; - PVR_ASSERT(psHashTab != IMG_NULL); + if (psHashTab == IMG_NULL) + { + return PVRSRV_ERROR_INIT_FAILURE; + } psPerProc = (PVRSRV_PER_PROCESS_DATA *)HASH_Retrieve(psHashTab, (IMG_UINTPTR_T)ui32PID); diff --git a/drivers/gpu/pvr/pvr_bridge_km.h b/drivers/gpu/pvr/pvr_bridge_km.h index c1fd04cb312..1175b76c194 100644 --- a/drivers/gpu/pvr/pvr_bridge_km.h +++ b/drivers/gpu/pvr/pvr_bridge_km.h @@ -109,7 +109,7 @@ PVRSRV_ERROR IMG_CALLCONV _PVRSRVAllocDeviceMemKM(IMG_HANDLE hDevCookie, #if defined(PVRSRV_LOG_MEMORY_ALLOCS) #define PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo, logStr) \ (PVR_TRACE(("PVRSRVAllocDeviceMemKM(" #devCookie ", " #perProc ", " #devMemHeap ", " #flags ", " #size \ - ", " #alignment "," #memInfo "): " logStr " (size = 0x%;x)", size)),\ + ", " #alignment "," #memInfo "): " logStr " (size = 0x%x)", size)),\ _PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo)) #else #define PVRSRVAllocDeviceMemKM(devCookie, perProc, devMemHeap, flags, size, alignment, memInfo, logStr) \ diff --git a/drivers/gpu/pvr/pvr_debug.c b/drivers/gpu/pvr/pvr_debug.c index 091f6590e70..2e64fe6ed36 100644 --- a/drivers/gpu/pvr/pvr_debug.c +++ b/drivers/gpu/pvr/pvr_debug.c @@ -1,6 +1,6 @@ /********************************************************************** * - * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. + * Copyright (C) Imagination Technologies Ltd. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -312,7 +312,8 @@ IMG_VOID PVRSRVDebugPrintf ( IMG_CHAR* pszTruncBackInter; - pszFileName = pszFullFileName + strlen(DEBUG_LOG_PATH_TRUNCATE)+1; + if (strlen(pszFullFileName) > strlen(DEBUG_LOG_PATH_TRUNCATE)+1) + pszFileName = pszFullFileName + strlen(DEBUG_LOG_PATH_TRUNCATE)+1; strncpy(szFileNameRewrite, pszFileName,PVR_MAX_FILEPATH_LEN); diff --git a/drivers/gpu/pvr/pvrversion.h b/drivers/gpu/pvr/pvrversion.h index 8c4505e2832..0e6e0e48929 100644 --- a/drivers/gpu/pvr/pvrversion.h +++ b/drivers/gpu/pvr/pvrversion.h @@ -30,8 +30,8 @@ #define PVRVERSION_MAJ 1 #define PVRVERSION_MIN 7 #define PVRVERSION_BRANCH 17 -#define PVRVERSION_BUILD 3957 -#define PVRVERSION_STRING "1.7.17.3957" +#define PVRVERSION_BUILD 4403 +#define PVRVERSION_STRING "1.7.17.4403" #define PVRVERSION_FILE "eurasiacon.pj" #endif diff --git a/drivers/gpu/pvr/resman.c b/drivers/gpu/pvr/resman.c index 5230952be84..b3a4534c809 100644 --- a/drivers/gpu/pvr/resman.c +++ b/drivers/gpu/pvr/resman.c @@ -122,7 +122,7 @@ static IMPLEMENT_LIST_INSERT(RESMAN_CONTEXT) #define PRINT_RESLIST(x, y, z) -static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem, IMG_BOOL bExecuteCallback); +static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem, IMG_BOOL bExecuteCallback, IMG_BOOL bForceCleanup); static PVRSRV_ERROR FreeResourceByCriteria(PRESMAN_CONTEXT psContext, IMG_UINT32 ui32SearchCriteria, @@ -379,7 +379,7 @@ PRESMAN_ITEM ResManRegisterRes(PRESMAN_CONTEXT psResManContext, return(psNewResItem); } -PVRSRV_ERROR ResManFreeResByPtr(RESMAN_ITEM *psResItem) +PVRSRV_ERROR ResManFreeResByPtr(RESMAN_ITEM *psResItem, IMG_BOOL bForceCleanup) { PVRSRV_ERROR eError; @@ -401,7 +401,7 @@ PVRSRV_ERROR ResManFreeResByPtr(RESMAN_ITEM *psResItem) VALIDATERESLIST(); - eError = FreeResourceByPtr(psResItem, IMG_TRUE); + eError = FreeResourceByPtr(psResItem, IMG_TRUE, bForceCleanup); VALIDATERESLIST(); @@ -478,7 +478,7 @@ PVRSRV_ERROR ResManDissociateRes(RESMAN_ITEM *psResItem, } else { - eError = FreeResourceByPtr(psResItem, IMG_FALSE); + eError = FreeResourceByPtr(psResItem, IMG_FALSE, CLEANUP_WITH_POLL); if(eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "ResManDissociateRes: failed to free resource by pointer")); @@ -554,9 +554,10 @@ IMG_INTERNAL PVRSRV_ERROR ResManFindResourceByPtr(PRESMAN_CONTEXT psResManContex } static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem, - IMG_BOOL bExecuteCallback) + IMG_BOOL bExecuteCallback, + IMG_BOOL bForceCleanup) { - PVRSRV_ERROR eError; + PVRSRV_ERROR eError = PVRSRV_OK; PVR_ASSERT(psItem != IMG_NULL); @@ -591,7 +592,7 @@ static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem, if (bExecuteCallback) { - eError = psItem->pfnFreeResource(psItem->pvParam, psItem->ui32Param); + eError = psItem->pfnFreeResource(psItem->pvParam, psItem->ui32Param, bForceCleanup); if (eError != PVRSRV_OK) { PVR_DPF((PVR_DBG_ERROR, "FreeResourceByPtr: ERROR calling FreeResource function")); @@ -602,11 +603,7 @@ static PVRSRV_ERROR FreeResourceByPtr(RESMAN_ITEM *psItem, ACQUIRE_SYNC_OBJ; - eError = OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(RESMAN_ITEM), psItem, IMG_NULL); - if (eError != PVRSRV_OK) - { - PVR_DPF((PVR_DBG_ERROR, "FreeResourceByPtr: ERROR freeing resource list item memory")); - } + OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(RESMAN_ITEM), psItem, IMG_NULL); return(eError); } @@ -667,7 +664,7 @@ static PVRSRV_ERROR FreeResourceByCriteria(PRESMAN_CONTEXT psResManContext, ui32Param)) != IMG_NULL && eError == PVRSRV_OK) { - eError = FreeResourceByPtr(psCurItem, bExecuteCallback); + eError = FreeResourceByPtr(psCurItem, bExecuteCallback, CLEANUP_WITH_POLL); } return eError; diff --git a/drivers/gpu/pvr/resman.h b/drivers/gpu/pvr/resman.h index 11af49be72d..c20719fe446 100644 --- a/drivers/gpu/pvr/resman.h +++ b/drivers/gpu/pvr/resman.h @@ -76,7 +76,7 @@ enum { #define RESMAN_CRITERIA_PVOID_PARAM 0x00000002 #define RESMAN_CRITERIA_UI32_PARAM 0x00000004 -typedef PVRSRV_ERROR (*RESMAN_FREE_FN)(IMG_PVOID pvParam, IMG_UINT32 ui32Param); +typedef PVRSRV_ERROR (*RESMAN_FREE_FN)(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bForceCleanup); typedef struct _RESMAN_ITEM_ *PRESMAN_ITEM; typedef struct _RESMAN_CONTEXT_ *PRESMAN_CONTEXT; @@ -90,7 +90,8 @@ PRESMAN_ITEM ResManRegisterRes(PRESMAN_CONTEXT hResManContext, IMG_UINT32 ui32Param, RESMAN_FREE_FN pfnFreeResource); -PVRSRV_ERROR ResManFreeResByPtr(PRESMAN_ITEM psResItem); +PVRSRV_ERROR ResManFreeResByPtr(PRESMAN_ITEM psResItem, + IMG_BOOL bForceCleanup); PVRSRV_ERROR ResManFreeResByCriteria(PRESMAN_CONTEXT hResManContext, IMG_UINT32 ui32SearchCriteria, diff --git a/drivers/gpu/pvr/services.h b/drivers/gpu/pvr/services.h index 3539e26448a..c61313a5f11 100644 --- a/drivers/gpu/pvr/services.h +++ b/drivers/gpu/pvr/services.h @@ -1066,6 +1066,10 @@ IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyMutex(PVRSRV_MUTEX_HANDLE hMut IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVLockMutex(PVRSRV_MUTEX_HANDLE hMutex); IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVUnlockMutex(PVRSRV_MUTEX_HANDLE hMutex); +IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVLockProcessGlobalMutex(void); +IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVUnlockProcessGlobalMutex(void); + + struct _PVRSRV_SEMAPHORE_OPAQUE_STRUCT_; typedef struct _PVRSRV_SEMAPHORE_OPAQUE_STRUCT_ *PVRSRV_SEMAPHORE_HANDLE; diff --git a/drivers/gpu/pvr/servicesext.h b/drivers/gpu/pvr/servicesext.h index 9a494b3dbcf..fdd63cb62fc 100644 --- a/drivers/gpu/pvr/servicesext.h +++ b/drivers/gpu/pvr/servicesext.h @@ -587,7 +587,13 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ { PVRSRV_PIXEL_FORMAT_C1_4KYUV420_2P_VU = 218, PVRSRV_PIXEL_FORMAT_P208 = 219, PVRSRV_PIXEL_FORMAT_A8P8 = 220, - + + PVRSRV_PIXEL_FORMAT_A4 = 221, + PVRSRV_PIXEL_FORMAT_AYUV8888 = 222, + PVRSRV_PIXEL_FORMAT_RAW256 = 223, + PVRSRV_PIXEL_FORMAT_RAW512 = 224, + PVRSRV_PIXEL_FORMAT_RAW1024 = 225, + PVRSRV_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff } PVRSRV_PIXEL_FORMAT; @@ -779,47 +785,6 @@ typedef struct ACCESS_INFO_TAG }ACCESS_INFO; -typedef struct PVRSRV_CURSOR_SHAPE_TAG -{ - IMG_UINT16 ui16Width; - IMG_UINT16 ui16Height; - IMG_INT16 i16XHot; - IMG_INT16 i16YHot; - - - IMG_VOID* pvMask; - IMG_INT16 i16MaskByteStride; - - - IMG_VOID* pvColour; - IMG_INT16 i16ColourByteStride; - PVRSRV_PIXEL_FORMAT eColourPixelFormat; -} PVRSRV_CURSOR_SHAPE; - -#define PVRSRV_SET_CURSOR_VISIBILITY (1<<0) -#define PVRSRV_SET_CURSOR_POSITION (1<<1) -#define PVRSRV_SET_CURSOR_SHAPE (1<<2) -#define PVRSRV_SET_CURSOR_ROTATION (1<<3) - -typedef struct PVRSRV_CURSOR_INFO_TAG -{ - - IMG_UINT32 ui32Flags; - - - IMG_BOOL bVisible; - - - IMG_INT16 i16XPos; - IMG_INT16 i16YPos; - - - PVRSRV_CURSOR_SHAPE sCursorShape; - - - IMG_UINT32 ui32Rotation; - -} PVRSRV_CURSOR_INFO; #if defined(PDUMP_SUSPEND_IS_PER_THREAD) typedef struct { diff --git a/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c b/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c index 03343e8ed14..9591c55a731 100644 --- a/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c +++ b/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c @@ -49,6 +49,7 @@ #include "bridged_pvr_bridge.h" #include "bridged_sgx_bridge.h" #include "sgxutils.h" +#include "buffer_manager.h" #include "pdump_km.h" static IMG_INT @@ -2185,7 +2186,8 @@ SGXUnregisterHWRenderContextBW(IMG_UINT32 ui32BridgeID, return 0; } - psRetOUT->eError = SGXUnregisterHWRenderContextKM(hHWRenderContextInt); + psRetOUT->eError = SGXUnregisterHWRenderContextKM(hHWRenderContextInt, + psSGXUnregHWRenderContextIN->bForceCleanup); if(psRetOUT->eError != PVRSRV_OK) { return 0; @@ -2270,7 +2272,8 @@ SGXUnregisterHWTransferContextBW(IMG_UINT32 ui32BridgeID, return 0; } - psRetOUT->eError = SGXUnregisterHWTransferContextKM(hHWTransferContextInt); + psRetOUT->eError = SGXUnregisterHWTransferContextKM(hHWTransferContextInt, + psSGXUnregHWTransferContextIN->bForceCleanup); if(psRetOUT->eError != PVRSRV_OK) { return 0; @@ -2352,7 +2355,8 @@ SGXUnregisterHW2DContextBW(IMG_UINT32 ui32BridgeID, return 0; } - psRetOUT->eError = SGXUnregisterHW2DContextKM(hHW2DContextInt); + psRetOUT->eError = SGXUnregisterHW2DContextKM(hHW2DContextInt, + psSGXUnregHW2DContextIN->bForceCleanup); if(psRetOUT->eError != PVRSRV_OK) { return 0; @@ -2386,7 +2390,7 @@ SGXFlushHWRenderTargetBW(IMG_UINT32 ui32BridgeID, return 0; } - SGXFlushHWRenderTargetKM(hDevCookieInt, psSGXFlushHWRenderTargetIN->sHWRTDataSetDevVAddr); + psRetOUT->eError = SGXFlushHWRenderTargetKM(hDevCookieInt, psSGXFlushHWRenderTargetIN->sHWRTDataSetDevVAddr, IMG_FALSE); return 0; } diff --git a/drivers/gpu/pvr/sgx/mmu.c b/drivers/gpu/pvr/sgx/mmu.c index 5a087cd449e..974973a5c28 100644 --- a/drivers/gpu/pvr/sgx/mmu.c +++ b/drivers/gpu/pvr/sgx/mmu.c @@ -79,6 +79,8 @@ typedef struct _MMU_PT_INFO_ IMG_VOID *hPTPageOSMemHandle; IMG_CPU_VIRTADDR PTPageCpuVAddr; + + IMG_UINT32 ui32ValidPTECount; } MMU_PT_INFO; @@ -2167,7 +2169,8 @@ MMU_UnmapPagesAndFreePTs (MMU_HEAP *psMMUHeap, - if (ppsPTInfoList[0] && ppsPTInfoList[0]->ui32ValidPTECount == 0) + if (ppsPTInfoList[0] && (ppsPTInfoList[0]->ui32ValidPTECount == 0) + ) { #if defined(FIX_HW_BRN_31620) if (BRN31620FreePageTable(psMMUHeap, ui32PDIndex) == IMG_TRUE) diff --git a/drivers/gpu/pvr/sgx/mmu.h b/drivers/gpu/pvr/sgx/mmu.h index d224f649667..59b24c44ad8 100644 --- a/drivers/gpu/pvr/sgx/mmu.h +++ b/drivers/gpu/pvr/sgx/mmu.h @@ -145,6 +145,8 @@ IMG_VOID MMU_GetCacheFlushRange(MMU_CONTEXT *pMMUContext, IMG_UINT32 *pui32Range IMG_VOID MMU_GetPDPhysAddr(MMU_CONTEXT *pMMUContext, IMG_DEV_PHYADDR *psDevPAddr); #endif + + #if defined(PDUMP) IMG_UINT32 MMU_GetPDumpContextID(IMG_HANDLE hDevMemContext); #endif diff --git a/drivers/gpu/pvr/sgx/pb.c b/drivers/gpu/pvr/sgx/pb.c index d9825c726a3..ab6523a9927 100644 --- a/drivers/gpu/pvr/sgx/pb.c +++ b/drivers/gpu/pvr/sgx/pb.c @@ -47,8 +47,8 @@ static IMPLEMENT_LIST_REMOVE(PVRSRV_STUB_PBDESC) static PRESMAN_ITEM psResItemCreateSharedPB = IMG_NULL; static PVRSRV_PER_PROCESS_DATA *psPerProcCreateSharedPB = IMG_NULL; -static PVRSRV_ERROR SGXCleanupSharedPBDescCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param); -static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param); +static PVRSRV_ERROR SGXCleanupSharedPBDescCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bDummy); +static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bDummy); IMG_EXPORT PVRSRV_ERROR SGXFindSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc, @@ -217,22 +217,24 @@ SGXCleanupSharedPBDescKM(PVRSRV_STUB_PBDESC *psStubPBDescIn) SGXCleanupRequest(psDeviceNode, &sHWPBDescDevVAddr, - PVRSRV_CLEANUPCMD_PB); + PVRSRV_CLEANUPCMD_PB, + CLEANUP_WITH_POLL); } return PVRSRV_OK; } -static PVRSRV_ERROR SGXCleanupSharedPBDescCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param) +static PVRSRV_ERROR SGXCleanupSharedPBDescCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bDummy) { PVRSRV_STUB_PBDESC *psStubPBDesc = (PVRSRV_STUB_PBDESC *)pvParam; PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); return SGXCleanupSharedPBDescKM(psStubPBDesc); } -static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param) +static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param, IMG_BOOL bDummy) { #ifdef DEBUG PVRSRV_PER_PROCESS_DATA *psPerProc = (PVRSRV_PER_PROCESS_DATA *)pvParam; @@ -242,6 +244,7 @@ static PVRSRV_ERROR SGXCleanupSharedPBDescCreateLockCallback(IMG_PVOID pvParam, #endif PVR_UNREFERENCED_PARAMETER(ui32Param); + PVR_UNREFERENCED_PARAMETER(bDummy); psPerProcCreateSharedPB = IMG_NULL; psResItemCreateSharedPB = IMG_NULL; @@ -255,7 +258,7 @@ SGXUnrefSharedPBDescKM(IMG_HANDLE hSharedPBDesc) { PVR_ASSERT(hSharedPBDesc != IMG_NULL); - return ResManFreeResByPtr(hSharedPBDesc); + return ResManFreeResByPtr(hSharedPBDesc, CLEANUP_WITH_POLL); } @@ -287,7 +290,7 @@ SGXAddSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc, { PVR_ASSERT(psResItemCreateSharedPB != IMG_NULL); - ResManFreeResByPtr(psResItemCreateSharedPB); + ResManFreeResByPtr(psResItemCreateSharedPB, CLEANUP_WITH_POLL); PVR_ASSERT(psResItemCreateSharedPB == IMG_NULL); PVR_ASSERT(psPerProcCreateSharedPB == IMG_NULL); diff --git a/drivers/gpu/pvr/sgx/sgxinit.c b/drivers/gpu/pvr/sgx/sgxinit.c index f4d37fb1dab..edc56b60f78 100644 --- a/drivers/gpu/pvr/sgx/sgxinit.c +++ b/drivers/gpu/pvr/sgx/sgxinit.c @@ -1426,6 +1426,16 @@ PVRSRV_ERROR SGX_FreeMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode, } #endif +static IMG_VOID SGXCacheInvalidate(PVRSRV_DEVICE_NODE *psDeviceNode) +{ + PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; + + #if defined(SGX_FEATURE_MP) + psDevInfo->ui32CacheControl |= SGXMKIF_CC_INVAL_BIF_SL; + #else + PVR_UNREFERENCED_PARAMETER(psDevInfo); + #endif +} PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode) { @@ -1498,6 +1508,8 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode) psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete; + psDeviceNode->pfnCacheInvalidate = SGXCacheInvalidate; + psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; diff --git a/drivers/gpu/pvr/sgx/sgxtransfer.c b/drivers/gpu/pvr/sgx/sgxtransfer.c index d0d09bf8237..f125a3f26a3 100644 --- a/drivers/gpu/pvr/sgx/sgxtransfer.c +++ b/drivers/gpu/pvr/sgx/sgxtransfer.c @@ -61,6 +61,8 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF IMG_UINT32 ui32RealSrcSyncNum = 0; IMG_BOOL abDstSyncEnable[SGX_MAX_TRANSFER_SYNC_OPS]; IMG_UINT32 ui32RealDstSyncNum = 0; + + #if defined(PDUMP) IMG_BOOL bPersistentProcess = IMG_FALSE; @@ -76,6 +78,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF hDevMemContext = psKick->hDevMemContext; #endif PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_ENTER, TRANSFER_TOKEN_SUBMIT); + for (loop = 0; loop < SGX_MAX_TRANSFER_SYNC_OPS; loop++) { abSrcSyncEnable[loop] = IMG_TRUE; @@ -189,6 +192,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF psSharedTransferCmd->ui32NumSrcSyncs = ui32RealSrcSyncNum; psSharedTransferCmd->ui32NumDstSyncs = ui32RealDstSyncNum; + if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL) { IMG_UINT32 i = 0; @@ -196,11 +200,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF for (loop = 0; loop < psKick->ui32NumSrcSync; loop++) { if (abSrcSyncEnable[loop]) - { - psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; - PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_SRC_SYNC, - psSyncInfo, PVRSRV_SYNCOP_SAMPLE); + PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_SRC_SYNC, + psSyncInfo, PVRSRV_SYNCOP_SAMPLE); psSharedTransferCmd->asSrcSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; psSharedTransferCmd->asSrcSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; @@ -216,11 +220,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF for (loop = 0; loop < psKick->ui32NumDstSync; loop++) { if (abDstSyncEnable[loop]) - { - psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; - PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_DST_SYNC, - psSyncInfo, PVRSRV_SYNCOP_SAMPLE); + PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_DST_SYNC, + psSyncInfo, PVRSRV_SYNCOP_SAMPLE); psSharedTransferCmd->asDstSyncs[i].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; psSharedTransferCmd->asDstSyncs[i].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; @@ -228,8 +232,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF psSharedTransferCmd->asDstSyncs[i].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; psSharedTransferCmd->asDstSyncs[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; i++; - - } + } } PVR_ASSERT(i == ui32RealDstSyncNum); @@ -237,17 +240,17 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF for (loop = 0; loop < psKick->ui32NumSrcSync; loop++) { if (abSrcSyncEnable[loop]) - { - psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; - psSyncInfo->psSyncData->ui32ReadOpsPending++; - } + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; + psSyncInfo->psSyncData->ui32ReadOpsPending++; + } } for (loop = 0; loop < psKick->ui32NumDstSync; loop++) { if (abDstSyncEnable[loop]) - { - psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; - psSyncInfo->psSyncData->ui32WriteOpsPending++; + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; + psSyncInfo->psSyncData->ui32WriteOpsPending++; } } } @@ -272,74 +275,73 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF for (loop = 0; loop < psKick->ui32NumSrcSync; loop++) { if (abSrcSyncEnable[loop]) - { - psSyncInfo = psKick->ahSrcSyncInfo[loop]; - - PDUMPCOMMENT("Hack src surface write op in transfer cmd\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, - psCCBMemInfo, + { + psSyncInfo = psKick->ahSrcSyncInfo[loop]; + + PDUMPCOMMENT("Hack src surface write op in transfer cmd\r\n"); + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, + psCCBMemInfo, psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)), - sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), - psKick->ui32PDumpFlags, - MAKEUNIQUETAG(psCCBMemInfo)); + sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), + psKick->ui32PDumpFlags, + MAKEUNIQUETAG(psCCBMemInfo)); - PDUMPCOMMENT("Hack src surface read op in transfer cmd\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, - psCCBMemInfo, + PDUMPCOMMENT("Hack src surface read op in transfer cmd\r\n"); + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, + psCCBMemInfo, psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal)), - sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), - psKick->ui32PDumpFlags, - MAKEUNIQUETAG(psCCBMemInfo)); - + sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), + psKick->ui32PDumpFlags, + MAKEUNIQUETAG(psCCBMemInfo)); i++; + } } - } + i = 0; for (loop = 0; loop < psKick->ui32NumDstSync; loop++) - { - if (abDstSyncEnable[i]) { - psSyncInfo = psKick->ahDstSyncInfo[loop]; - - PDUMPCOMMENT("Hack dest surface write op in transfer cmd\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, - psCCBMemInfo, + if (abDstSyncEnable[i]) + { + psSyncInfo = psKick->ahDstSyncInfo[loop]; + + PDUMPCOMMENT("Hack dest surface write op in transfer cmd\r\n"); + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, + psCCBMemInfo, psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)), - sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), - psKick->ui32PDumpFlags, - MAKEUNIQUETAG(psCCBMemInfo)); + sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), + psKick->ui32PDumpFlags, + MAKEUNIQUETAG(psCCBMemInfo)); - PDUMPCOMMENT("Hack dest surface read op in transfer cmd\r\n"); - PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, - psCCBMemInfo, + PDUMPCOMMENT("Hack dest surface read op in transfer cmd\r\n"); + PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, + psCCBMemInfo, psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + i * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal)), - sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), - psKick->ui32PDumpFlags, - MAKEUNIQUETAG(psCCBMemInfo)); - + sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), + psKick->ui32PDumpFlags, + MAKEUNIQUETAG(psCCBMemInfo)); i++; + } } - } - + for (loop = 0; loop < (psKick->ui32NumSrcSync); loop++) - { + { if (abSrcSyncEnable[loop]) { - psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; - psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; + psSyncInfo->psSyncData->ui32LastReadOpDumpVal++; + } } - } for (loop = 0; loop < (psKick->ui32NumDstSync); loop++) - { - if (abDstSyncEnable[loop]) { - psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[0]; - psSyncInfo->psSyncData->ui32LastOpDumpVal++; + if (abDstSyncEnable[loop]) + { + psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[0]; + psSyncInfo->psSyncData->ui32LastOpDumpVal++; + } } } - } } #endif @@ -360,13 +362,13 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (abSrcSyncEnable[loop]) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; - psSyncInfo->psSyncData->ui32ReadOpsPending--; + psSyncInfo->psSyncData->ui32ReadOpsPending--; #if defined(PDUMP) - if (PDumpIsCaptureFrameKM() - || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) - { - psSyncInfo->psSyncData->ui32LastReadOpDumpVal--; - } + if (PDumpIsCaptureFrameKM() + || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) + { + psSyncInfo->psSyncData->ui32LastReadOpDumpVal--; + } #endif } } @@ -380,10 +382,10 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (PDumpIsCaptureFrameKM() || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) { - psSyncInfo->psSyncData->ui32LastOpDumpVal--; - } + psSyncInfo->psSyncData->ui32LastOpDumpVal--; + } #endif - } + } } } @@ -420,8 +422,8 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (abSrcSyncEnable[loop]) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; - psSyncInfo->psSyncData->ui32ReadOpsComplete = psSyncInfo->psSyncData->ui32ReadOpsPending; - } + psSyncInfo->psSyncData->ui32ReadOpsComplete = psSyncInfo->psSyncData->ui32ReadOpsPending; + } } for (loop = 0; loop < psKick->ui32NumDstSync; loop++) @@ -429,8 +431,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF if (abDstSyncEnable[loop]) { psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; - psSyncInfo->psSyncData->ui32WriteOpsComplete = psSyncInfo->psSyncData->ui32WriteOpsPending; - + psSyncInfo->psSyncData->ui32WriteOpsComplete = psSyncInfo->psSyncData->ui32WriteOpsPending; } } diff --git a/drivers/gpu/pvr/sgx/sgxutils.c b/drivers/gpu/pvr/sgx/sgxutils.c index cf7ecc68d93..75b1b893200 100644 --- a/drivers/gpu/pvr/sgx/sgxutils.c +++ b/drivers/gpu/pvr/sgx/sgxutils.c @@ -206,7 +206,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode, - if ( (eCmdType != SGXMKIF_CMD_PROCESS_QUEUES) && + if ( (eCmdType != SGXMKIF_CMD_PROCESS_QUEUES) && ((psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_DATA) != 0) && ((psDevInfo->ui32CacheControl & (SGXMKIF_CC_INVAL_BIF_PT | SGXMKIF_CC_INVAL_BIF_PD)) != 0)) { @@ -227,7 +227,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode, { goto Exit; } - + #if !defined(NO_HARDWARE) if(PollForValueKM(&psSGXHostCtl->ui32InvalStatus, @@ -241,7 +241,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode, PVR_DBG_BREAK; } #endif - + #if defined(PDUMP) PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for BIF cache invalidate request to complete"); @@ -253,14 +253,14 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode, 0, MAKEUNIQUETAG(psSGXHostCtlMemInfo)); #endif - + psSGXHostCtl->ui32InvalStatus &= ~(PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE); PDUMPMEM(IMG_NULL, psSGXHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psSGXHostCtlMemInfo)); } -#else +#else PVR_UNREFERENCED_PARAMETER(hDevMemContext); #endif - + #if defined(FIX_HW_BRN_31620) if ((eCmdType != SGXMKIF_CMD_FLUSHPDCACHE) && (psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_BIF_PD)) { @@ -636,9 +636,10 @@ PVRSRV_ERROR SGXGetInternalDevInfoKM(IMG_HANDLE hDevCookie, } -IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, - IMG_DEV_VIRTADDR *psHWDataDevVAddr, - IMG_UINT32 ui32CleanupType) +PVRSRV_ERROR SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, + IMG_DEV_VIRTADDR *psHWDataDevVAddr, + IMG_UINT32 ui32CleanupType, + IMG_BOOL bForceCleanup) { PVRSRV_ERROR eError; PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; @@ -647,52 +648,64 @@ IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, SGXMKIF_COMMAND sCommand = {0}; - sCommand.ui32Data[0] = ui32CleanupType; - sCommand.ui32Data[1] = (psHWDataDevVAddr == IMG_NULL) ? 0 : psHWDataDevVAddr->uiAddr; - PDUMPCOMMENTWITHFLAGS(0, "Request ukernel resource clean-up, Type %u, Data 0x%X", sCommand.ui32Data[0], sCommand.ui32Data[1]); - eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0, IMG_NULL, IMG_FALSE); - if (eError != PVRSRV_OK) + if (bForceCleanup != FORCE_CLEANUP) { - PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command")); - PVR_DBG_BREAK; - } - + sCommand.ui32Data[0] = ui32CleanupType; + sCommand.ui32Data[1] = (psHWDataDevVAddr == IMG_NULL) ? 0 : psHWDataDevVAddr->uiAddr; + PDUMPCOMMENTWITHFLAGS(0, "Request ukernel resource clean-up, Type %u, Data 0x%X", sCommand.ui32Data[0], sCommand.ui32Data[1]); - #if !defined(NO_HARDWARE) - if(PollForValueKM(&psHostCtl->ui32CleanupStatus, - PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, - PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, - 10 * MAX_HW_TIME_US, - 1000, - IMG_TRUE) != PVRSRV_OK) - { - PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType)); - PVR_DBG_BREAK; - } - #endif + eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0, IMG_NULL, IMG_FALSE); + if (eError != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command")); + PVR_DBG_BREAK; + return eError; + } - #if defined(PDUMP) - - PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for clean-up request to complete"); - PDUMPMEMPOL(psHostCtlMemInfo, - offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), - PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, - PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, - PDUMP_POLL_OPERATOR_EQUAL, - 0, - MAKEUNIQUETAG(psHostCtlMemInfo)); - #endif + #if !defined(NO_HARDWARE) + if(PollForValueKM(&psHostCtl->ui32CleanupStatus, + PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, + PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, + 10 * MAX_HW_TIME_US, + 1000, + IMG_TRUE) != PVRSRV_OK) + { + PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType)); + eError = PVRSRV_ERROR_TIMEOUT; + PVR_DBG_BREAK; + } + #endif + + #if defined(PDUMP) + + PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for clean-up request to complete"); + PDUMPMEMPOL(psHostCtlMemInfo, + offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), + PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, + PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, + PDUMP_POLL_OPERATOR_EQUAL, + 0, + MAKEUNIQUETAG(psHostCtlMemInfo)); + #endif + + if (eError != PVRSRV_OK) + { + return eError; + } + } + psHostCtl->ui32CleanupStatus &= ~(PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE); PDUMPMEM(IMG_NULL, psHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psHostCtlMemInfo)); - + #if defined(SGX_FEATURE_SYSTEM_CACHE) psDevInfo->ui32CacheControl |= (SGXMKIF_CC_INVAL_BIF_SL | SGXMKIF_CC_INVAL_DATA); #else psDevInfo->ui32CacheControl |= SGXMKIF_CC_INVAL_DATA; #endif + return PVRSRV_OK; } @@ -706,15 +719,18 @@ typedef struct _SGX_HW_RENDER_CONTEXT_CLEANUP_ static PVRSRV_ERROR SGXCleanupHWRenderContextCallback(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) + IMG_UINT32 ui32Param, + IMG_BOOL bForceCleanup) { + PVRSRV_ERROR eError; SGX_HW_RENDER_CONTEXT_CLEANUP *psCleanup = pvParam; PVR_UNREFERENCED_PARAMETER(ui32Param); - SGXCleanupRequest(psCleanup->psDeviceNode, + eError = SGXCleanupRequest(psCleanup->psDeviceNode, &psCleanup->sHWRenderContextDevVAddr, - PVRSRV_CLEANUPCMD_RC); + PVRSRV_CLEANUPCMD_RC, + bForceCleanup); OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_RENDER_CONTEXT_CLEANUP), @@ -722,7 +738,7 @@ static PVRSRV_ERROR SGXCleanupHWRenderContextCallback(IMG_PVOID pvParam, psCleanup->hBlockAlloc); - return PVRSRV_OK; + return eError; } typedef struct _SGX_HW_TRANSFER_CONTEXT_CLEANUP_ @@ -735,15 +751,18 @@ typedef struct _SGX_HW_TRANSFER_CONTEXT_CLEANUP_ static PVRSRV_ERROR SGXCleanupHWTransferContextCallback(IMG_PVOID pvParam, - IMG_UINT32 ui32Param) + IMG_UINT32 ui32Param, + IMG_BOOL bForceCleanup) { + PVRSRV_ERROR eError; SGX_HW_TRANSFER_CONTEXT_CLEANUP *psCleanup = (SGX_HW_TRANSFER_CONTEXT_CLEANUP *)pvParam; PVR_UNREFERENCED_PARAMETER(ui32Param); - SGXCleanupRequest(psCleanup->psDeviceNode, + eError = SGXCleanupRequest(psCleanup->psDeviceNode, &psCleanup->sHWTransferContextDevVAddr, - PVRSRV_CLEANUPCMD_TC); + PVRSRV_CLEANUPCMD_TC, + bForceCleanup); OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_TRANSFER_CONTEXT_CLEANUP), @@ -751,7 +770,7 @@ static PVRSRV_ERROR SGXCleanupHWTransferContextCallback(IMG_PVOID pvParam, psCleanup->hBlockAlloc); - return PVRSRV_OK; + return eError; } IMG_EXPORT @@ -804,7 +823,7 @@ IMG_HANDLE SGXRegisterHWRenderContextKM(IMG_HANDLE psDeviceNode, } IMG_EXPORT -PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext) +PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext, IMG_BOOL bForceCleanup) { PVRSRV_ERROR eError; SGX_HW_RENDER_CONTEXT_CLEANUP *psCleanup; @@ -819,7 +838,7 @@ PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext) return PVRSRV_ERROR_INVALID_PARAMS; } - eError = ResManFreeResByPtr(psCleanup->psResItem); + eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup); return eError; } @@ -875,7 +894,7 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode, } IMG_EXPORT -PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext) +PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext, IMG_BOOL bForceCleanup) { PVRSRV_ERROR eError; SGX_HW_TRANSFER_CONTEXT_CLEANUP *psCleanup; @@ -890,7 +909,7 @@ PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext) return PVRSRV_ERROR_INVALID_PARAMS; } - eError = ResManFreeResByPtr(psCleanup->psResItem); + eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup); return eError; } @@ -904,15 +923,19 @@ typedef struct _SGX_HW_2D_CONTEXT_CLEANUP_ PRESMAN_ITEM psResItem; } SGX_HW_2D_CONTEXT_CLEANUP; -static PVRSRV_ERROR SGXCleanupHW2DContextCallback(IMG_PVOID pvParam, IMG_UINT32 ui32Param) +static PVRSRV_ERROR SGXCleanupHW2DContextCallback(IMG_PVOID pvParam, + IMG_UINT32 ui32Param, + IMG_BOOL bForceCleanup) { + PVRSRV_ERROR eError; SGX_HW_2D_CONTEXT_CLEANUP *psCleanup = (SGX_HW_2D_CONTEXT_CLEANUP *)pvParam; PVR_UNREFERENCED_PARAMETER(ui32Param); - SGXCleanupRequest(psCleanup->psDeviceNode, + eError = SGXCleanupRequest(psCleanup->psDeviceNode, &psCleanup->sHW2DContextDevVAddr, - PVRSRV_CLEANUPCMD_2DC); + PVRSRV_CLEANUPCMD_2DC, + bForceCleanup); OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(SGX_HW_2D_CONTEXT_CLEANUP), @@ -920,7 +943,7 @@ static PVRSRV_ERROR SGXCleanupHW2DContextCallback(IMG_PVOID pvParam, IMG_UINT32 psCleanup->hBlockAlloc); - return PVRSRV_OK; + return eError; } IMG_EXPORT @@ -973,7 +996,7 @@ IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE psDeviceNode, } IMG_EXPORT -PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext) +PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext, IMG_BOOL bForceCleanup) { PVRSRV_ERROR eError; SGX_HW_2D_CONTEXT_CLEANUP *psCleanup; @@ -987,7 +1010,7 @@ PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext) psCleanup = (SGX_HW_2D_CONTEXT_CLEANUP *)hHW2DContext; - eError = ResManFreeResByPtr(psCleanup->psResItem); + eError = ResManFreeResByPtr(psCleanup->psResItem, bForceCleanup); return eError; } @@ -1076,13 +1099,16 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo, IMG_EXPORT -IMG_VOID SGXFlushHWRenderTargetKM(IMG_HANDLE psDeviceNode, IMG_DEV_VIRTADDR sHWRTDataSetDevVAddr) +PVRSRV_ERROR SGXFlushHWRenderTargetKM(IMG_HANDLE psDeviceNode, + IMG_DEV_VIRTADDR sHWRTDataSetDevVAddr, + IMG_BOOL bForceCleanup) { PVR_ASSERT(sHWRTDataSetDevVAddr.uiAddr != IMG_NULL); - SGXCleanupRequest(psDeviceNode, + return SGXCleanupRequest(psDeviceNode, &sHWRTDataSetDevVAddr, - PVRSRV_CLEANUPCMD_RT); + PVRSRV_CLEANUPCMD_RT, + bForceCleanup); } @@ -1141,7 +1167,7 @@ PVRSRV_ERROR SGXContextSuspend(PVRSRV_DEVICE_NODE *psDeviceNode, PVR_DPF((PVR_DBG_ERROR,"SGXContextSuspend: Failed to submit context suspend command")); return eError; } - + return eError; } diff --git a/drivers/gpu/pvr/sgx/sgxutils.h b/drivers/gpu/pvr/sgx/sgxutils.h index a7cbcb7193a..bc60fdd9186 100644 --- a/drivers/gpu/pvr/sgx/sgxutils.h +++ b/drivers/gpu/pvr/sgx/sgxutils.h @@ -75,13 +75,15 @@ IMG_HANDLE SGXRegisterHWTransferContextKM(IMG_HANDLE psDeviceNode, PVRSRV_PER_PROCESS_DATA *psPerProc); IMG_IMPORT -IMG_VOID SGXFlushHWRenderTargetKM(IMG_HANDLE psSGXDevInfo, IMG_DEV_VIRTADDR psHWRTDataSetDevVAddr); +PVRSRV_ERROR SGXFlushHWRenderTargetKM(IMG_HANDLE psSGXDevInfo, + IMG_DEV_VIRTADDR psHWRTDataSetDevVAddr, + IMG_BOOL bForceCleanup); IMG_IMPORT -PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext); +PVRSRV_ERROR SGXUnregisterHWRenderContextKM(IMG_HANDLE hHWRenderContext, IMG_BOOL bForceCleanup); IMG_IMPORT -PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext); +PVRSRV_ERROR SGXUnregisterHWTransferContextKM(IMG_HANDLE hHWTransferContext, IMG_BOOL bForceCleanup); #if defined(SGX_FEATURE_2D_HARDWARE) IMG_IMPORT @@ -90,16 +92,17 @@ IMG_HANDLE SGXRegisterHW2DContextKM(IMG_HANDLE psDeviceNode, PVRSRV_PER_PROCESS_DATA *psPerProc); IMG_IMPORT -PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext); +PVRSRV_ERROR SGXUnregisterHW2DContextKM(IMG_HANDLE hHW2DContext, IMG_BOOL bForceCleanup); #endif IMG_UINT32 SGXConvertTimeStamp(PVRSRV_SGXDEV_INFO *psDevInfo, IMG_UINT32 ui32TimeWraps, IMG_UINT32 ui32Time); -IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, +PVRSRV_ERROR SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode, IMG_DEV_VIRTADDR *psHWDataDevVAddr, - IMG_UINT32 ui32CleanupType); + IMG_UINT32 ui32CleanupType, + IMG_BOOL bForceCleanup); IMG_IMPORT PVRSRV_ERROR PVRSRVGetSGXRevDataKM(PVRSRV_DEVICE_NODE* psDeviceNode, IMG_UINT32 *pui32SGXCoreRev, diff --git a/drivers/gpu/pvr/sgx535defs.h b/drivers/gpu/pvr/sgx520defs.h index 66f216668a0..a21295d0c64 100644 --- a/drivers/gpu/pvr/sgx535defs.h +++ b/drivers/gpu/pvr/sgx520defs.h @@ -24,12 +24,10 @@ * ******************************************************************************/ -#ifndef _SGX535DEFS_KM_H_ -#define _SGX535DEFS_KM_H_ +#ifndef _SGX520DEFS_KM_H_ +#define _SGX520DEFS_KM_H_ #define EUR_CR_CLKGATECTL 0x0000 -#define EUR_CR_CLKGATECTL_2D_CLKG_MASK 0x00000003U -#define EUR_CR_CLKGATECTL_2D_CLKG_SHIFT 0 #define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000030U #define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 4 #define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000300U @@ -43,8 +41,6 @@ #define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U #define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 #define EUR_CR_CLKGATESTATUS 0x0004 -#define EUR_CR_CLKGATESTATUS_2D_CLKS_MASK 0x00000001 -#define EUR_CR_CLKGATESTATUS_2D_CLKS_SHIFT 0 #define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000010U #define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 4 #define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000100U @@ -56,8 +52,6 @@ #define EUR_CR_CLKGATESTATUS_USE_CLKS_MASK 0x00100000U #define EUR_CR_CLKGATESTATUS_USE_CLKS_SHIFT 20 #define EUR_CR_CLKGATECTLOVR 0x0008 -#define EUR_CR_CLKGATECTLOVR_2D_CLKO_MASK 0x00000003U -#define EUR_CR_CLKGATECTLOVR_2D_CLKO_SHIFT 0 #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000030U #define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 4 #define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000300U @@ -91,8 +85,6 @@ #define EUR_CR_SOFT_RESET 0x0080 #define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U #define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0 -#define EUR_CR_SOFT_RESET_TWOD_RESET_MASK 0x00000002U -#define EUR_CR_SOFT_RESET_TWOD_RESET_SHIFT 1 #define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U #define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2 #define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00000008U @@ -104,65 +96,45 @@ #define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000040U #define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 6 #define EUR_CR_EVENT_HOST_ENABLE2 0x0110 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_HOST_ENABLE2_BIF_REQUESTER_FAULT_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_ENABLE2_BIF_REQUESTER_FAULT_SHIFT 4 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_SHIFT 2 +#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U +#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4 +#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U +#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3 +#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U +#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2 #define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U #define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0 #define EUR_CR_EVENT_HOST_CLEAR2 0x0114 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_HOST_CLEAR2_BIF_REQUESTER_FAULT_MASK 0x00000010U -#define EUR_CR_EVENT_HOST_CLEAR2_BIF_REQUESTER_FAULT_SHIFT 4 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_SHIFT 2 +#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U +#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4 +#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U +#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3 +#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U +#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2 #define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U #define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_STATUS2 0x0118U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000080U -#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 7 -#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000040U -#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 6 -#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000020U -#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 5 -#define EUR_CR_EVENT_STATUS2_BIF_REQUESTER_FAULT_MASK 0x00000010U -#define EUR_CR_EVENT_STATUS2_BIF_REQUESTER_FAULT_SHIFT 4 -#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U -#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_SHIFT 3 -#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_MASK 0x00000004U -#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_SHIFT 2 +#define EUR_CR_EVENT_STATUS2 0x0118 +#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U +#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4 +#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U +#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3 +#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U +#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2 #define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U #define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1 #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U #define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0 -#define EUR_CR_EVENT_STATUS 0x012CU +#define EUR_CR_EVENT_STATUS 0x012C #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U #define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31 #define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U #define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29 #define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U #define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27 #define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U #define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26 #define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U @@ -224,8 +196,6 @@ #define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29 #define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U #define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27 #define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U #define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26 #define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U @@ -287,8 +257,6 @@ #define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29 #define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U #define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28 -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U -#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27 #define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U #define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26 #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U @@ -343,11 +311,94 @@ #define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1 #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U #define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0 +#define EUR_CR_TIMER 0x0144 +#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU +#define EUR_CR_TIMER_VALUE_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_0 0x0A0C +#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_1 0x0A10 +#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_2 0x0A14 +#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_3 0x0A18 +#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_4 0x0A1C +#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_5 0x0A20 +#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_6 0x0A24 +#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_7 0x0A28 +#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_8 0x0A2C +#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_9 0x0A30 +#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_10 0x0A34 +#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_11 0x0A38 +#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_12 0x0A3C +#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_13 0x0A40 +#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_14 0x0A44 +#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 20 +#define EUR_CR_USE_CODE_BASE_15 0x0A48 +#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x000FFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0 +#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 20 #define EUR_CR_PDS_EXEC_BASE 0x0AB8 -#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0xFFF00000U +#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20 #define EUR_CR_EVENT_KICKER 0x0AC4 -#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U +#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U #define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4 #define EUR_CR_EVENT_KICK 0x0AC8 #define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U @@ -392,8 +443,6 @@ #define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9 #define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U #define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_MASK 0x00000800U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_SHIFT 11 #define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U #define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12 #define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U @@ -402,8 +451,6 @@ #define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14 #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U #define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15 -#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_MASK 0x00010000U -#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_SHIFT 16 #define EUR_CR_BIF_INT_STAT 0x0C04 #define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU #define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0 @@ -412,237 +459,28 @@ #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U #define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15 #define EUR_CR_BIF_FAULT 0x0C08 -#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U +#define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U #define EUR_CR_BIF_FAULT_ADDR_SHIFT 12 -#define EUR_CR_BIF_TILE0 0x0C0C -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE0_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE1 0x0C10 -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE1_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE2 0x0C14 -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE2_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE3 0x0C18 -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE3_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE4 0x0C1C -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE4_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE5 0x0C20 -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE5_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE6 0x0C24 -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE6_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE7 0x0C28 -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE7_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE8 0x0C2C -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE8_CFG_SHIFT 24 -#define EUR_CR_BIF_TILE9 0x0C30 -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU -#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0 -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U -#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12 -#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U -#define EUR_CR_BIF_TILE9_CFG_SHIFT 24 -#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38 -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40 -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44 -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48 -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50 -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE8 0x0C54 -#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE9 0x0C58 -#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE10 0x0C5C -#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE11 0x0C60 -#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE12 0x0C64 -#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE13 0x0C68 -#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE14 0x0C6C -#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_SHIFT 12 -#define EUR_CR_BIF_DIR_LIST_BASE15 0x0C70 -#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_MASK 0xFFFFF000U -#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_SHIFT 12 -#define EUR_CR_BIF_BANK_SET 0x0C74 -#define EUR_CR_BIF_BANK_SET_SELECT_MASK 0x000003FFU -#define EUR_CR_BIF_BANK_SET_SELECT_SHIFT 0 -#define EUR_CR_BIF_BANK0 0x0C78 -#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK0_INDEX_HOST_MASK 0x00000F00U -#define EUR_CR_BIF_BANK0_INDEX_HOST_SHIFT 8 -#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK0_INDEX_2D_MASK 0x000F0000U -#define EUR_CR_BIF_BANK0_INDEX_2D_SHIFT 16 -#define EUR_CR_BIF_BANK1 0x0C7C -#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU -#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0 -#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U -#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4 -#define EUR_CR_BIF_BANK1_INDEX_HOST_MASK 0x00000F00U -#define EUR_CR_BIF_BANK1_INDEX_HOST_SHIFT 8 -#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U -#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12 -#define EUR_CR_BIF_BANK1_INDEX_2D_MASK 0x000F0000U -#define EUR_CR_BIF_BANK1_INDEX_2D_SHIFT 16 -#define EUR_CR_BIF_ADT_TTE 0x0C80 -#define EUR_CR_BIF_ADT_TTE_VALUE_MASK 0x000000FFU -#define EUR_CR_BIF_ADT_TTE_VALUE_SHIFT 0 #define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84 #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U #define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12 -#define EUR_CR_BIF_TWOD_REQ_BASE 0x0C88 -#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK 0xFFF00000U -#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_SHIFT 20 #define EUR_CR_BIF_TA_REQ_BASE 0x0C90 -#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U +#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1 0x0C94 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_MMU_MASK 0x00000007U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_MMU_SHIFT 0 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_CACHE_MASK 0x00000038U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_CACHE_SHIFT 3 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_VDM_MASK 0x000001C0U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_VDM_SHIFT 6 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TE_MASK 0x00000E00U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TE_SHIFT 9 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TWOD_MASK 0x00007000U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TWOD_SHIFT 12 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_PBE_MASK 0x00038000U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_PBE_SHIFT 15 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2 0x0C98 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_HOST_MASK 0x00000007U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_HOST_SHIFT 0 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_USE_MASK 0x00000038U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_USE_SHIFT 3 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_ISP_MASK 0x000001C0U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_ISP_SHIFT 6 -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_TSPP_MASK 0x00000E00U -#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_TSPP_SHIFT 9 -#define EUR_CR_BIF_MEM_ARB_CONFIG 0x0CA0 -#define EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_MASK 0x0000000FU -#define EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT 0 -#define EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_MASK 0x00000FF0U -#define EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT 4 -#define EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_MASK 0x00FFF000U -#define EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT 12 #define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8 #define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU #define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0 #define EUR_CR_BIF_3D_REQ_BASE 0x0CAC -#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U +#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20 #define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0 -#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U +#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U #define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20 -#define EUR_CR_BIF_BANK_STATUS 0x0CB4 -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U -#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0 -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U -#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 -#define EUR_CR_2D_BLIT_STATUS 0x0E04 -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU -#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 -#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U -#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24 -#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10 -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U -#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4 -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U -#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12 -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U -#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24 -#define EUR_CR_2D_SOCIF 0x0E18 -#define EUR_CR_2D_SOCIF_FREESPACE_MASK 0x000000FFU -#define EUR_CR_2D_SOCIF_FREESPACE_SHIFT 0 -#define EUR_CR_2D_ALPHA 0x0E1C -#define EUR_CR_2D_ALPHA_COMPONENT_ONE_MASK 0x0000FF00U -#define EUR_CR_2D_ALPHA_COMPONENT_ONE_SHIFT 8 -#define EUR_CR_2D_ALPHA_COMPONENT_ZERO_MASK 0x000000FFU -#define EUR_CR_2D_ALPHA_COMPONENT_ZERO_SHIFT 0 #define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) -#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x01FFFFFFU +#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x000FFFFFU #define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 -#define EUR_CR_USE_CODE_BASE_DM_MASK 0x06000000U -#define EUR_CR_USE_CODE_BASE_DM_SHIFT 25 +#define EUR_CR_USE_CODE_BASE_DM_MASK 0x00300000U +#define EUR_CR_USE_CODE_BASE_DM_SHIFT 20 #define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16 #define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16 diff --git a/drivers/gpu/pvr/sgx544defs.h b/drivers/gpu/pvr/sgx544defs.h index ff3e1e05da6..c18b8ad042a 100644 --- a/drivers/gpu/pvr/sgx544defs.h +++ b/drivers/gpu/pvr/sgx544defs.h @@ -987,6 +987,22 @@ #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 #define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 +#define EUR_CR_BIF_MMU_CTRL 0x0CD0 +#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U +#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0 +#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0 +#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U +#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1 +#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0 +#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U +#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3 +#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0 +#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U +#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4 +#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0 +#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_MASK 0x00000020U +#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SHIFT 5 +#define EUR_CR_BIF_MMU_CTRL_DISABLE_BURST_EXP_SIGNED 0 #define EUR_CR_2D_BLIT_STATUS 0x0E04 #define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU #define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 diff --git a/drivers/gpu/pvr/sgx_bridge.h b/drivers/gpu/pvr/sgx_bridge.h index 926c75b69f4..204189c1d18 100644 --- a/drivers/gpu/pvr/sgx_bridge.h +++ b/drivers/gpu/pvr/sgx_bridge.h @@ -521,6 +521,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT_TAG typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT_TAG { IMG_UINT32 ui32BridgeFlags; + IMG_BOOL bForceCleanup; #if defined (SUPPORT_SID_INTERFACE) IMG_SID hDevCookie; IMG_SID hHWRenderContext; @@ -554,6 +555,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT_TAG { IMG_UINT32 ui32BridgeFlags; + IMG_BOOL bForceCleanup; #if defined (SUPPORT_SID_INTERFACE) IMG_SID hDevCookie; IMG_SID hHWTransferContext; @@ -600,6 +602,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT_TAG typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT_TAG { IMG_UINT32 ui32BridgeFlags; + IMG_BOOL bForceCleanup; #if defined (SUPPORT_SID_INTERFACE) IMG_SID hDevCookie; IMG_SID hHW2DContext; diff --git a/drivers/gpu/pvr/sgxerrata.h b/drivers/gpu/pvr/sgxerrata.h index de8f484c8a6..83c0444cc9f 100644 --- a/drivers/gpu/pvr/sgxerrata.h +++ b/drivers/gpu/pvr/sgxerrata.h @@ -406,6 +406,18 @@ #define FIX_HW_BRN_31425 #endif #else + #if SGX_CORE_REV == 104 + #define FIX_HW_BRN_29954 + #define FIX_HW_BRN_31093 + #define FIX_HW_BRN_31195 + #define FIX_HW_BRN_31278 + #if defined(SGX_FEATURE_MP) + #define FIX_HW_BRN_31425 + #endif + #define FIX_HW_BRN_31542 + #define FIX_HW_BRN_31620 + #define FIX_HW_BRN_31671 + #else #if SGX_CORE_REV == 105 #if defined(SGX_FEATURE_MP) #define FIX_HW_BRN_31425 @@ -420,6 +432,7 @@ #endif #endif #endif + #endif #define SGX_CORE_DEFINED #endif @@ -471,19 +484,12 @@ #define SGX_CORE_REV SGX_CORE_REV_HEAD #endif - #if SGX_CORE_REV == 100 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #else - #if SGX_CORE_REV == 101 - #if defined(SGX_FEATURE_MP) - #define FIX_HW_BRN_31425 - #endif - #else #if SGX_CORE_REV == 123 #else + #if SGX_CORE_REV == 124 + + #else #if SGX_CORE_REV == SGX_CORE_REV_HEAD #else @@ -491,7 +497,6 @@ #endif #endif #endif - #endif #define SGX_CORE_DEFINED #endif |