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Unify the MOCS to be more consistently across the platforms.
Currently gen8+ are specifyig UC whereas earlier platforms
generally use PTE. Let's make everyone more or less specify
L3+PTE.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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Create a gen9 specific struct so that the gen-9+ Yf/Ys tiling bits can be
added there.
Suggested-by: Katarzyna Dec <katarzyna.dec@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Instead of using definitions duplicated in gen7_render header,
we should use the oldest definition that is working with chosen
gen. This patch reuse gen6 definitons if registers/fields/shifts
that were introduced in other genX_render headers.
v3: Rebase and checkpatch
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Populate the gen8+ SURFACE_STATE aux bits correctly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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gen8 introduces 48 bit virtual addresses. Set both dwords correctly
as otherwise the presumed_offset will not match what we actually
have stored in the surface state if the buffer is located somewhere
above 4GiB.
I guess we're not currently using 48bit addresses with rendercopy?
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
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This patch implements some changes in gen8_render header and
all files that include it. Renamed all definition that were
introduced in that file with prefix GEN8_* instead of
previous GEN's one if they were not implemented there,
otherwise dropped duplicates. Modified include to use
gen7_render header instead of gen6.
v2: Fixed commit message
v3: fixed typo in commit msg
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ewelina Musial <ewelina.musial@intel.com>
Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
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Previously we didn't have a clear understanding what is necessary
for a pipeline state to be properly initialized. So we had to improvise
and use a stripped out render copy.
Now we have a more clear understanding so switch out render copy based
frankenstate to state we can call golden state.
v2: - export intel_batch_state_offset
- add 3DSTATE_RASTER (Bradley Volkin)
Cc: Volkin, Bradley D <bradley.d.volkin@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
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rendercopy was failing to emit 3DSTATE_WM_DEPTH_STENCIL, which is a new
packet on Broadwell. Mesa emits this packet.
This appears to fix various tests on a fresh boot, when Mesa has never
run.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78890
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Guo Jinxian <jinxianx.guo@intel.com>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
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Using uint64_t in that second member makes it aligned to 64bits, while
the first member is only 32bits. We then had a 32bits hole in there!
Found-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Rafael Barbalho <rafael.barbalho@intel.com>
Tested-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
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We don't want depth/stencil fast clears or HiZ resolves; we want normal
drawing. Without this, the pixel pipeline doesn't work.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Damien Lespiau <damien.lespiau@intel.com>
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For posterity, I've squashed these commits against Damien's request.
rendercopy/gen8: Fix the include guards
rendercopy/gen8: Update the 3DSTATE_MULTISAMPLE opcode
The opcode has changed in BDW.
rendercopy/gen8: Add the VF_TOPOLOGY state
The primitive type has moved out of the 3DPRIMITIVE to its own state,
VF_TOPOLOGY.
rendercopy/gen8: Fixup 3STATE_PS
Update the state to the latest BSpec, in particular the thread count was
using a wrong shift and we were missing kernel2 offset.
rendercopy/gen8: Update 3DSTATE_BASE_ADDRESS
This state has seen its fields moved around a bit, follow the BSpec.
rendercopy/gen8: Allocate 64 VUEs
The simulator screams at us if we try to allocate less than that.
rendercopy/gen8: Surface states have to be 64 bytes a aligned
rendercopy/gen8: Vertical/horizontal align 2 does not exist any more
So set them to 4. This should not matter with rendercopy (which is not
using compressed textures), but it makes the simulator moan.
rendercopy/gen8: Make sure the vertex buffer is 8 bytes aligned
rendercopy/gen8: Adjust 3DSTATE_VERTEX_BUFFERS for gen8
The address of the buffer is now on 48 bits. Also the size was computed
as offset + size where the field is really the size of the buffer
itself, not the end address.
rendercopy/gen8: Update the SF/SBE states for gen8
gen8 has a few changes around those states and a new ones RASTER and
SBE_SWIZ.
rendercopy/gen8: Add the PS_EXTRA and PS_BLEND states
rendercopy/gen8: Fix building with DEBUG_RENDERCOPY defined
The forward declaration was missing the final ';'. Let's move the whole
function at the top instead.
rendercopy/gen8: Update the PS and CONSTANT_PS states
rendercopy/gen8: Fix the red channel selection
Make it output red.
rendercopy/gen8: Update the write -1 shader
With the latest assembler changes from Haihao.
rendercopy/gen8: Remove blit.g8a
There is no diff between this file and blig.g7a. Remove it.
rendercopy/gen8: Fix the surface relocation offset
The surface base address is now at dwords 8/9 so the relocation has to
mirror the change.
rendercopy/gen8: Add the VF_INSTANCING state
Should work without, but doesn't hurt to add it.
rendercopy/gen8: Set the Attribule enable field in PS_EXTRA
When the SF is set up to output some attributes, the pixel shader also
have to be told there's attributes to care about.
rendercopy/gen8: Set the force bits to read URB offset/length
If we want to override the URB offset/length in the SBE state itself, we
need to set the force bits on (new in gen8)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
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Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
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