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2019-04-29lib/rendercopy: Configure MOCS more consistentlyVille Syrjälä
Unify the MOCS to be more consistently across the platforms. Currently gen8+ are specifyig UC whereas earlier platforms generally use PTE. Let's make everyone more or less specify L3+PTE. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-04-29lib/rendercopy: Add fp16 support for gen4+Ville Syrjälä
Allow copying between fp16 surfaces. We'll use the FLOAT surface format since that's all the display supports currently. Hopefully the hardware gives us a 1:1 copy, at least if the input doesn't contain crazy infs/nans etc. We could choose UNORM instead but that won't work for eventually exposing fp16+ccs. Although we do need to replace the simple bpp value with a more specific format type to get 10bpc+ccs working as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2019-04-04lib/rendercopy: Assert that buffer dimensions/stride are acceptableVille Syrjälä
Sprinkle some asserts into rendercopy to make sure we don't try to exceed the render engine surface size/stride limitations. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-11-20lib/rendercopy: Implement support for 8/16 bppMaarten Lankhorst
To handle drawing 16 bpp formats correctly with odd x/w, we need to use the correct bpp to rendercopy. Now that everything sets bpp in igt_buf, fix the rendercopy support to use it and set the correct format. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [mlankhorst: Add assert(src->bpp == dst->bpp)]
2018-10-04lib/i915: Move shaders directoryKatarzyna Dec
In shaders/ directory we got Intel specific information. As igt is a project for more vendors, let's move this directory to lib/i915. v2: Changed shaders directory path in library files comments. Signed-off-by: Katarzyna Dec <katarzyna.dec@intel.com> Cc: Arkadiusz Hiler <arkadiusz.hiler@intel.com> Cc: Petri Latvala <petri.latvala@intel.com> Cc: Kalamarz Lukasz <lukasz.kalamarz@intel.com> Cc: Antonio Argenziano <antonio.argenziano@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-07-18lib/rendercopy: Use gen4 definitions if applicableLukasz Kalamarz
Instead of using definitions duplicated in gen7_render header, we should use the oldest definition that is working with chosen gen. This patch reuse gen6 definitons if registers/fields/shifts that were introduced in other genX_render headers. v3: Rebase and checkpatch Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com> Cc: Katarzyna Dec <katarzyna.dec@intel.com> Cc: Antonio Argenziano <antonio.argenziano@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
2018-07-06lib/rendercopy: Set the upper 32bits of surface base address on gen8+Ville Syrjälä
gen8 introduces 48 bit virtual addresses. Set both dwords correctly as otherwise the presumed_offset will not match what we actually have stored in the surface state if the buffer is located somewhere above 4GiB. I guess we're not currently using 48bit addresses with rendercopy? Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-07-05lib: Constify igt_bufVille Syrjälä
No one generally needs to modify the igt_bufs we pass around, so make them const. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-07-03lib/rendercopy: Simplify reloc offsetsVille Syrjälä
Remove the hardcoded dword offsets for the relocs and instead rely fully on intel_batchbuffer_subdata_offset(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-07-03lib/rendercopy: Use gen8_wm_kernel__affineChris Wilson
The shaders/blit.g7a has weird artefacts (random pixel kill) when drawing to an odd destination coordinate. Rather than debug the issue with the asm/assembler, replace the kernel with the one used by SNA for simple copies. Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com> #chv, skl Acked-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2018-06-14lib/gen8_render: Cleanup of libsLukasz Kalamarz
This patch implements some changes in gen8_render header and all files that include it. Renamed all definition that were introduced in that file with prefix GEN8_* instead of previous GEN's one if they were not implemented there, otherwise dropped duplicates. Modified include to use gen7_render header instead of gen6. v2: Fixed commit message v3: fixed typo in commit msg Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com> Cc: Katarzyna Dec <katarzyna.dec@intel.com> Cc: Antonio Argenziano <antonio.argenziano@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Ewelina Musial <ewelina.musial@intel.com> Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
2018-06-14lib/rendercopy: Use gen6 definitions if applicableLukasz Kalamarz
Instead of using definitions duplicated in gen7_render header, we should use the oldest definition that is working with chosen gen. This patch reuses gen6 definitons if registers/fields/shifts that were reintroduced in other genX_render headers. v2: Fixed commit message v3: fixed typos in commit msg Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com> Cc: Katarzyna Dec <katarzyna.dec@intel.com> Cc: Antonio Argenziano <antonio.argenziano@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Ewelina Musial <ewelina.musial@intel.com> Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
2018-06-05lib: Rename all surfaceformat calls in libsLukasz Kalamarz
This patch is renaming all surfaceformat registers to use names introduced in surfaceformat.h instead of using per gen definitions v2: Drop GEN_ from register names. Applied that to other libs. Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com> Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
2018-04-24lib/intel_batchbuffer: Move batch functions from media/render/gpgpu libsKalamarz, Lukasz
Batch functions were copy/pasted across several libs. With moving it into intel_batchbuffer lib test can now be easly maintained without worrying that we forgot to modify older version of lib. v2: Added documentation into lib and rebased patch v3: Fixed typos and rebased patch v4: Fixed documentation issues v5: Rename, clean up of leftovers from previous version and documentation polishing v6: Fixing assert Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com> Cc: Katarzyna Dec <katarzyna.dec@intel.com> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Katarzyna Dec <katarzyna.dec@intel.com>
2017-12-07lib: copy intel_aub.h from libdrmScott D Phillips
No functionality related to aub is provided by libdrm aside from intel_aub.h which somewhat defines the file format. Move the header into this project to ease aub-related development. Signed-off-by: Scott D Phillips <scott.d.phillips@intel.com> Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2016-11-09Revert "lib: use the local intel_aub.h file"Tomeu Vizoso
Emil prefers if the approach in v2 is used (it was sent around the time v1 had been applied). This reverts commit 438c8d7c688780337d271016d84a69aab0474097.
2016-10-27lib: use the local intel_aub.h fileEmil Velikov
File is provided by the libdrm_intel package which is optional. Since we already have a local copy of the file, we might as well use it ;-) Cc: Brian Starkey <brian.starkey@arm.com> Reported-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-03-26igt.cocci: check the return values of various functionsThomas Wood
Add rules to fix unused-result warnings when compiling with _FORTIFY_SOURCE defined and apply them to the library and tests. Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
2014-12-18lib/gen8: Make rendercopy threadsafeChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-09-05lib/rendercopy: fix a typo in defineMika Kuoppala
No functional changes Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
2014-09-01rendercopy/gen8: Fix vertex buffer relocationChris Wilson
I was thrown by the routine calling itself gen7 when in it gen8 specific and required 64bit relocation fixes. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-08-29Prepare for 64bit relocation addressesChris Wilson
This reveal that quite a few locations were writing relocation offsets but only allowing for 32 bit addresses. To reveal such places in active tests, we also now double check that we do not use more batch space than declared. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2014-08-26lib/rendercopy*: Use igt_assertDaniel Vetter
2014-07-23tests: remove unused getopt header includesThomas Wood
Signed-off-by: Thomas Wood <thomas.wood@intel.com>
2014-06-12lib: remove /** from comments that are not API documentationThomas Wood
These comments are not gtk-doc comments, so replacing /** with /* prevents any gtk-doc warnings. Signed-off-by: Thomas Wood <thomas.wood@intel.com>
2014-06-04rendercopy/gen8: Also emit 3DSTATE_WM_DEPTH_STENCIL.Kenneth Graunke
rendercopy was failing to emit 3DSTATE_WM_DEPTH_STENCIL, which is a new packet on Broadwell. Mesa emits this packet. This appears to fix various tests on a fresh boot, when Mesa has never run. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78890 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78891 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78935 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78936 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78937 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78938 Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: Guo Jinxian <jinxianx.guo@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2014-04-24tests: Extract ALIGN macro into a common headerTvrtko Ursulin
Makes for a little bit less code duplication, especially since it will be used from more callers in the future. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Brad Volkin <bradley.d.volkin@intel.com> Signed-off-by: Thomas Wood <thomas.wood@intel.com>
2014-03-23lib: extract igt_aux.[hc]Daniel Vetter
And shovel all the various helpers in there. Also move igt_set_vt_graphics_mode to igt_kms.h since the function is implemented in igt_kms.c. And it fits better. I kinda missed this in the prep work. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-22lib: s/drmtest_dumb_aub/igt_aub_dump_enabled/Daniel Vetter
This is prep work to extract a new igt aux library with all kinds of random stuff. Also give it a bit a more suitable name to indicate that this is just a flag and doesn't do the aub dumping itself. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-22lib: rename intel_gpu_tools.h to intel_io.hDaniel Vetter
With the header cleanup we can now give this header a suitable name, since it now really only contains register access and other I/O functions and assorted definitions. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-22lib: remove uncessary #includes from headersDaniel Vetter
Only include what the header itself needs. The big fish here is intel-gpu-tools.h. More will follow. One ugly thing removed here is the duplicated GEN6_TD_CTL #define, one of which was broken. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-22lib/intel_batchbuffer: igt_ namespace for the buffer structureDaniel Vetter
Step one to properly namespace the rendercpy/mediafill functions. Als give the buf_height/width helpers a proper igt_ prefix. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-03-22lib: make rendercopy.h an internal headerDaniel Vetter
And move the public interfaces into intel_batchbuffer.[hc]. A bit messy since we are fairly inconsistent with our header #include handling. Also exclude rendercopy.h from the documentation. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-12-10rendercopy/bdw: Fix length of a bunch of zeroed out packets.Kenneth Graunke
A bunch of packets were too short. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Damien Lespiau <damien.lespiau@intel.com>
2013-12-10rendercopy/bdw: Emit 3DSTATE_WM_HZ_OP.Kenneth Graunke
We don't want depth/stencil fast clears or HiZ resolves; we want normal drawing. Without this, the pixel pipeline doesn't work. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Damien Lespiau <damien.lespiau@intel.com>
2013-12-06rendercopy/bdw: Set Instruction Buffer size Modify Enable to 1Xiang, Haihao
Otherwise it may result in GPU hang Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-28rendercopy/bdw: Fix the 3DSTATE_STENCIL_BUFFER instruction lengthDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-28rendercopy/bdw: Fix the 3DSTATE_HIER_DEPTH_BUFFER instruction lengthDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-28rendercopy/bdw: Fix the various 3DSTATE_CONSTANT_* instruction lengthDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-28rendercopy/bdw: Fix the STATE_SIP instruction lengthDamien Lespiau
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-11-27rendercopy: Pass context to rendercopy functionsVille Syrjälä
rendercopy does the batch buffer flush internally, so if we want to use it with multiple contexts, we need to pass the context in from caller. v2: Modify rendercopy_gen8 as well Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2013-11-06rendercopy/bdw: Add AUB annotations for statesDamien Lespiau
This will hopefully help debugging things. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
2013-11-06rendercopy/bdw: Fix the original implementationDamien Lespiau
For posterity, I've squashed these commits against Damien's request. rendercopy/gen8: Fix the include guards rendercopy/gen8: Update the 3DSTATE_MULTISAMPLE opcode The opcode has changed in BDW. rendercopy/gen8: Add the VF_TOPOLOGY state The primitive type has moved out of the 3DPRIMITIVE to its own state, VF_TOPOLOGY. rendercopy/gen8: Fixup 3STATE_PS Update the state to the latest BSpec, in particular the thread count was using a wrong shift and we were missing kernel2 offset. rendercopy/gen8: Update 3DSTATE_BASE_ADDRESS This state has seen its fields moved around a bit, follow the BSpec. rendercopy/gen8: Allocate 64 VUEs The simulator screams at us if we try to allocate less than that. rendercopy/gen8: Surface states have to be 64 bytes a aligned rendercopy/gen8: Vertical/horizontal align 2 does not exist any more So set them to 4. This should not matter with rendercopy (which is not using compressed textures), but it makes the simulator moan. rendercopy/gen8: Make sure the vertex buffer is 8 bytes aligned rendercopy/gen8: Adjust 3DSTATE_VERTEX_BUFFERS for gen8 The address of the buffer is now on 48 bits. Also the size was computed as offset + size where the field is really the size of the buffer itself, not the end address. rendercopy/gen8: Update the SF/SBE states for gen8 gen8 has a few changes around those states and a new ones RASTER and SBE_SWIZ. rendercopy/gen8: Add the PS_EXTRA and PS_BLEND states rendercopy/gen8: Fix building with DEBUG_RENDERCOPY defined The forward declaration was missing the final ';'. Let's move the whole function at the top instead. rendercopy/gen8: Update the PS and CONSTANT_PS states rendercopy/gen8: Fix the red channel selection Make it output red. rendercopy/gen8: Update the write -1 shader With the latest assembler changes from Haihao. rendercopy/gen8: Remove blit.g8a There is no diff between this file and blig.g7a. Remove it. rendercopy/gen8: Fix the surface relocation offset The surface base address is now at dwords 8/9 so the relocation has to mirror the change. rendercopy/gen8: Add the VF_INSTANCING state Should work without, but doesn't hurt to add it. rendercopy/gen8: Set the Attribule enable field in PS_EXTRA When the SF is set up to output some attributes, the pixel shader also have to be told there's attributes to care about. rendercopy/gen8: Set the force bits to read URB offset/length If we want to override the URB offset/length in the SBE state itself, we need to set the force bits on (new in gen8) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Acked-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-06rendercopy/bdw: Initial gen8 rendercopyJesse Barnes
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
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