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2019-04-16lib/intel_reg: fix shift undefined behaviourSimon Ser
1<<31 (same as 2<<30) is undefined behaviour in C. When compiling with GCC and UBSan, it gives this error: ../tools/intel_reg_decode.c: In function ‘ivb_debug_port’: ../tools/intel_reg_decode.c:398:3: error: case label does not reduce to an integer constant case PORT_DBG_DRRS_HW_STATE_HIGH: ^~~~ This happens because 1<<31 isn't representable as a signed int. Instead, use an unsigned int. Signed-off-by: Simon Ser <simon.ser@intel.com> Reviewed-by: Petri Latvala <petri.latvala@intel.com>
2017-12-11igt_fb: Add support for drawing to non-32bit Y/Yf tiled FBsImre Deak
When drawing with cairo to Y/Yf tiled FBs we use a temporary linear buffer which is mapped to the CPU, but the fast blit needed for this only expects 32 bpp FBs. Add support for other bpps too. This is needed for upcoming patches testing non-32bit bpp formats with Y/Yf tiling. Thanks to Ville for explaining why we need the temporary buffer. (Looks like for Y tiling we could do without, but that's a separate topic.) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Imre Deak <imre.deak@intel.com>
2016-08-05tools/intel_reg: Dump DP_BUFTRANS registers on ILK-IVBVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2015-03-12lib/skl: Add gen9 specific igt_blitter_fast_copy()Damien Lespiau
v2: Adjust for BB handling changes. (Tvrtko Ursulin) Correct XY_FAST_COPY_DST_TILING_Yf. (Tvrtko Ursulin) v3: New tiling modes are not defined in the kernel any more. (Tvrtko Ursulin) Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
2015-01-12tools/intel_audio_dump: add support for CherryviewYang, Libin
This patch adds support for dumping audio registers of Cherryview. Signed-off-by: Libin Yang <libin.yang@intel.com>
2014-10-21tests/gem_exec_parse: test for chained batch buffersBrad Volkin
libva makes extensive use of chained batch buffers. The batch buffer copy portion of the command parser has the potential to break chained batches, so add a simple test to make sure that doesn't happen. Signed-off-by: Brad Volkin <bradley.d.volkin@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-09-05lib: Add MI_LOAD_REGISTER_IMMMika Kuoppala
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
2014-06-13tools/intel_display_poller: Add a new tool that will poll various display ↵Ville Syrjälä
registers intel_poller can be used to poll various display registers (IIR,scanline/pixel/flip/frame counter, live address, etc.). It can be used to determine eg. at which scanline or pixel count certain events occur. v2: s/intel_poller/intel_display_poller/ Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-06-12lib: remove /** from comments that are not API documentationThomas Wood
These comments are not gtk-doc comments, so replacing /** with /* prevents any gtk-doc warnings. Signed-off-by: Thomas Wood <thomas.wood@intel.com>
2014-06-03lib/intel_iosf: add second phy supportVille Syrjälä
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com>
2014-05-19igt/intel_iosf: rename IOSF sideband opcodes according to the specImre Deak
These opcodes are not specific for an endpoint, but are the same for all endpoints. So rename them accordingly, using the name the VLV2 sideband HAS uses. Also move the macros to the .c file, since they aren't used anywhere else. Signed-off-by: Imre Deak <imre.deak@intel.com>
2014-01-28mmio: use intel_iosf.c for DPIO reads and writesJesse Barnes
This makes it a bit more like the kernel, so we can go poke at DPIO and other IOSF regs a bit more easily. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2014-01-07lib: Move the INSTDONE bit definitions to instdone.cDamien Lespiau
This is the only place where they are used and we've even started using 1 << n constants with gen 7. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2014-01-07intel_reg: Renamed INST_DONE to INSTDONEDamien Lespiau
That's how the registers are named in the kernel defines. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
2013-12-06lib: rename some power well bit namesPaulo Zanoni
I did the same change in the Kernel a few months ago. This should help not getting confused about which bit does what. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2013-12-05Kill XY_COLOR_BLT_CMDBen Widawsky
Since we now always want a length for this command, and we've created a non-length variant, remove the #define to prevent further foot shooting. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-12-05gem_pipe_control_store_loop: BDW updateBen Widawsky
I've opted to not use the PIPE_CONTROL w/a for now. I am unclear if it is actually required (the test does pass). Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2013-11-20tools/reg_dumper: Add FW_BLC regsDaniel Vetter
Debugging watermark issues on gen2/3 without them is hard ... Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-11-06bdw: Update obvious missing blit supportBen Widawsky
This provides a macro that allows us to update all the arbitrary blit commands we have stuck throughout the code. It assumes we don't actually use 64b relocs (which is currently true). This also allows us to easily find all the areas we need to update later when we really use the upper dword. This block was done mostly with a sed job, and represents the easier in test blit implementations. v2 by Oscar: s/OUT_BATCH/BEGIN_BATCH in BLIT_COPY_BATCH_START CC: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
2013-07-09tools/intel_reg_dumper: add gen6+ fencesDaniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-03lib: fix WM_DBG register addressPaulo Zanoni
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2013-04-16add VLV punit & north cluster read toolsJesse Barnes
2013-04-09intel_reg_dumper: improve the dumping of backlight registersPaulo Zanoni
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2013-03-22intel_reg_dumper: dump HSW watermark registersPaulo Zanoni
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2013-03-22intel_reg_dumper: make Haswell dump usefulPaulo Zanoni
It was previously printing ironlake_debug_regs and haswell_debug_regs. Since ironlake_debug_regs contains a lot of registers that don't exist on Haswell, running intel_reg_dumper on Haswell caused "unclaimed register" messages. Now I've copied the existing registers from ironlake_debug_regs to haswell_debug_regs, so we won't print the registers that don't exist anymore. Also removed DP_TP_STATUS_A since it doesn't exist. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
2012-12-01tools/intel_reg_dumper: add some cpt/ppt debug regsDaniel Vetter
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-25s/NO_PID/NOP_IDDaniel Vetter
Alan typo'ed it, I've failed to notice :(
2012-08-24Rename NOPID to NO_PID to avoid conflict with Solaris NOPIDAlan Coopersmith
Solaris <sys/types.h> already has #define NOPID (pid_t)(-1) Signed-off-by: Alan Coopersmith <alan.coopersmith@oracle.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-21tools: Added intel_dpio_read and intel_dpio_writeVijay Purushothaman
In Valleyview the DPLL and lane control registers are accessible only through side band fabric called DPIO. Added two tools to read and write registers residing in this space. v2: Moved the core read/write functions to lib/intel_dpio.c based on Ben's feedback Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-08-08tools/reg_dumper: really dump pipe C regsDaniel Vetter
Not just a copy of pipe B. Meh. Also kill a few redudant #define for pipe B - they match pipe A.
2012-08-07tools/reg_dumper: dump pipe C regsDaniel Vetter
Also reorder the pipe B regs a bit to be consisten with pipe A.
2012-06-13intel_reg_dumper: dump more PM registersEugeni Dodonov
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-05-08tools: add Haswell registers into intel_reg_dumperEugeni Dodonov
For now, only print their content for diffing, but also add the necessary bits that can be used for more verbose output in the fugure. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-02-22intel_reg_dumper: Add dumping of GPU turbo regs.Eric Anholt
I was interested in finding why my IVB system is not getting GPU turbo after suspend/resume. The piece that looks weird to me is that INTERRUPT_THRESHOLD is sitting at 0, whereas pre-suspend it's 0x12000000.
2012-01-27intel_reg_dumper: add TRANS_VSYNCSHIFTDaniel Vetter
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2012-01-03tools/intel_reg_dumper: retrieve rc6 residency valuesEugeni Dodonov
This allows to check if rc6 works, and how long have we been in each state. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2012-01-03tools/intel_reg_dumper: Add support for debug registerEugeni Dodonov
Right now, we only check for hardware DRRS support. But much more can be done with it. Some day. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
2011-10-28intel_reg_dumper: handle 3 pipe configs when dumping HDMI configJesse Barnes
Could be on pipe A, B, or C. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-28intel-gpu-tools/debugging: add important debug regsBen Widawsky
Cc: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-24gem_stress: Add render copyfunc for SandyBridgeChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-16intel_disable_clock_gating: New tool for turning off clock gating on ILK.Eric Anholt
This is something I sometimes want to do in testing, to see if a mystery bug (say, 29172) is due to broken clock gating. Sadly, in this case it isn't. Note that it isn't supported on non-ILK chipsets yet.
2010-09-20intel_reg_dumper: eDP port is on the CPU, not PCHJesse Barnes
Made me think there was another register until I checked the offset.
2010-09-05reg dumper: Dump ILK panel fitting control debug registersChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-06-30intel_reg_dumper: add some 945 MI reg dumpingJesse Barnes
2010-04-15reg dump update for SNB/CPTZhenyu Wang
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-03-24Fix INSTDONE1 bits on g4x, and use those on Ironlake too.Eric Anholt
2010-03-24Add Ironlake INSTDONE bits.Eric Anholt
2010-02-25Add support for Sandybridge INSTDONE regs.Eric Anholt
2010-01-15reg_dump: Dump display port register on IronlakeZhao Yakui
Dump the display port register on Ironlake. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-06Add: tools/intel_audio_dumpWu Fengguang
Signed-off-by: Zhenyu Wang <zhenyu.z.wang@intel.com> Signed-off-by: Wu Fengguang <fengguang.wu@intel.com>
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